Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 441b78b0 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
Browse files

Merge "drm/msm/dp: update the DP catalog driver for sdmmagpie"

parents e385235d fac8afeb

drivers/gpu/drm/msm/dp/dp_catalog_v420.c

+30 −0
Original line number Diff line number Diff line
@@ -102,6 +102,34 @@ static void dp_catalog_aux_setup_v420(struct dp_catalog_aux *aux, 
			0x1F);

}



static void dp_catalog_aux_clear_hw_interrupts_v420(struct dp_catalog_aux *aux)

{

	struct dp_catalog_private_v420 *catalog;

	struct dp_io_data *io_data;

	u32 data = 0;



	if (!aux) {

		pr_err("invalid input\n");

		return;

	}



	catalog = dp_catalog_get_priv_v420(aux);

	io_data = catalog->io->dp_phy;



	data = dp_read(catalog->exe_mode, io_data,

		DP_PHY_AUX_INTERRUPT_STATUS_V420);



	dp_write(catalog->exe_mode, io_data,

		DP_PHY_AUX_INTERRUPT_CLEAR_V420, 0x1f);

	wmb(); /* make sure 0x1f is written before next write */

	dp_write(catalog->exe_mode, io_data,

		DP_PHY_AUX_INTERRUPT_CLEAR_V420, 0x9f);

	wmb(); /* make sure 0x9f is written before next write */

	dp_write(catalog->exe_mode, io_data,

		DP_PHY_AUX_INTERRUPT_CLEAR_V420, 0);

	wmb(); /* make sure register is cleared */

}



static void dp_catalog_panel_config_msa_v420(struct dp_catalog_panel *panel,

					u32 rate, u32 stream_rate_khz,

					bool fixed_nvid)
@@ -312,6 +340,8 @@ int dp_catalog_get_v420(struct device *dev, struct dp_catalog *catalog, 
	catalog->priv.set_exe_mode = dp_catalog_set_exe_mode_v420;



	catalog->aux.setup         = dp_catalog_aux_setup_v420;

	catalog->aux.clear_hw_interrupts =

				dp_catalog_aux_clear_hw_interrupts_v420;

	catalog->panel.config_msa  = dp_catalog_panel_config_msa_v420;

	catalog->ctrl.phy_lane_cfg = dp_catalog_ctrl_phy_lane_cfg_v420;

	catalog->ctrl.update_vx_px = dp_catalog_ctrl_update_vx_px_v420;

drivers/gpu/drm/msm/dp/dp_reg.h

+11 −9
Original line number Diff line number Diff line
@@ -269,9 +269,9 @@ 
#define DP_PHY_AUX_CFG7                         (0x0000003C)

#define DP_PHY_AUX_CFG8                         (0x00000040)

#define DP_PHY_AUX_CFG9                         (0x00000044)

#define DP_PHY_AUX_INTERRUPT_MASK               (0x00000054)

#define DP_PHY_AUX_INTERRUPT_CLEAR              (0x00000058)

#define DP_PHY_AUX_INTERRUPT_STATUS             (0x000000D8)

#define DP_PHY_AUX_INTERRUPT_MASK               (0x00000048)

#define DP_PHY_AUX_INTERRUPT_CLEAR              (0x0000004C)

#define DP_PHY_AUX_INTERRUPT_STATUS             (0x000000BC)

#define DP_PHY_AUX_INTERRUPT_MASK_V200          (0x00000048)

#define DP_PHY_AUX_INTERRUPT_CLEAR_V200         (0x0000004C)

#define DP_PHY_AUX_INTERRUPT_STATUS_V200        (0x000000BC)
@@ -282,6 +282,8 @@ 
#define TXn_TX_DRV_LVL				(0x001C)



#define DP_PHY_AUX_INTERRUPT_MASK_V420		(0x0054)

#define DP_PHY_AUX_INTERRUPT_CLEAR_V420		(0x0058)

#define DP_PHY_AUX_INTERRUPT_STATUS_V420	(0x00D8)

#define DP_PHY_SPARE0_V420			(0x00C8)

#define TXn_TX_DRV_LVL_V420			(0x0014)
@@ -290,16 +292,16 @@ 
/* DP MMSS_CC registers */

#define MMSS_DP_LINK_CMD_RCGR			(0x0138)

#define MMSS_DP_LINK_CFG_RCGR			(0x013C)

#define MMSS_DP_PIXEL_M				(0x0174)

#define MMSS_DP_PIXEL_N				(0x0178)

#define MMSS_DP_PIXEL_M				(0x01B4)

#define MMSS_DP_PIXEL_N				(0x01B8)

#define MMSS_DP_PIXEL1_M			(0x01CC)

#define MMSS_DP_PIXEL1_N			(0x01D0)

#define MMSS_DP_PIXEL_M_V200			(0x0130)

#define MMSS_DP_PIXEL_N_V200			(0x0134)

#define MMSS_DP_PIXEL_M_V420			(0x01B4)

#define MMSS_DP_PIXEL_N_V420			(0x01B8)

#define MMSS_DP_PIXEL1_M			(0x018C)

#define MMSS_DP_PIXEL1_N			(0x0190)

#define MMSS_DP_PIXEL1_M_V200			(0x0148)

#define MMSS_DP_PIXEL1_N_V200			(0x014C)

#define MMSS_DP_PIXEL_M_V420			(0x01B4)

#define MMSS_DP_PIXEL_N_V420			(0x01B8)

#define MMSS_DP_PIXEL1_M_V420			(0x01CC)

#define MMSS_DP_PIXEL1_N_V420			(0x01D0)