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Commit 44024ba7 authored by Taniya Das's avatar Taniya Das
Browse files

clk: qcom: videocc: Remove sleep clock for SM6150 



As the sleep clock is defined from the device tree, remove all instances of
the sleep clock from the video code. Also update the clock indexes
accordingly.

Change-Id: I225403f3c14bfc96d564a8ad2ab9520b347a7f50
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent ac66517d

drivers/clk/qcom/videocc-sm6150.c

+0 −16
Original line number Diff line number Diff line
@@ -118,15 +118,6 @@ static struct clk_alpha_pll video_pll0_out_main = { 
	},

};



/* chip_sleep_clk is external clocks running at 32000Hz */

static struct clk_fixed_rate chip_sleep_clk = {

	.fixed_rate = 32000,

	.hw.init = &(struct clk_init_data){

		.name = "chip_sleep_clk",

		.ops = &clk_fixed_rate_ops,

	},

};



static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] = {

	F(32000, P_CHIP_SLEEP_CLK, 1, 0, 0),

	{ }
@@ -142,7 +133,6 @@ static struct clk_rcg2 video_cc_sleep_clk_src = { 
		.name = "video_cc_sleep_clk_src",

		.parent_names = video_cc_parent_names_0,

		.num_parents = 2,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		.vdd_class = &vdd_cx,

		.num_rate_max = VDD_NUM,
@@ -334,10 +324,6 @@ static struct clk_branch video_cc_xo_clk = { 
	},

};



struct clk_hw *video_cc_sm6150_hws[] = {

	[CHIP_SLEEP_CLK] = &chip_sleep_clk.hw,

};



static struct clk_regmap *video_cc_sm6150_clocks[] = {

	[VIDEO_CC_APB_CLK] = &video_cc_apb_clk.clkr,

	[VIDEO_CC_SLEEP_CLK] = &video_cc_sleep_clk.clkr,
@@ -365,8 +351,6 @@ static const struct qcom_cc_desc video_cc_sm6150_desc = { 
	.config = &video_cc_sm6150_regmap_config,

	.clks = video_cc_sm6150_clocks,

	.num_clks = ARRAY_SIZE(video_cc_sm6150_clocks),

	.hwclks = video_cc_sm6150_hws,

	.num_hwclks = ARRAY_SIZE(video_cc_sm6150_hws),

};



static const struct of_device_id video_cc_sm6150_match_table[] = {

include/dt-bindings/clock/qcom,videocc-sm6150.h

+12 −15
Original line number Diff line number Diff line
@@ -14,21 +14,18 @@ 
#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM6150_H

#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM6150_H



/* Hardware clocks*/

#define CHIP_SLEEP_CLK						0



/* VIDEOCC clock registers */

#define VIDEO_PLL0_OUT_MAIN					1

#define VIDEO_CC_APB_CLK					2

#define VIDEO_CC_SLEEP_CLK					3

#define VIDEO_CC_SLEEP_CLK_SRC					4

#define VIDEO_CC_VCODEC0_AXI_CLK				5

#define VIDEO_CC_VCODEC0_CORE_CLK				6

#define VIDEO_CC_VENUS_AHB_CLK					7

#define VIDEO_CC_VENUS_CLK_SRC					8

#define VIDEO_CC_VENUS_CTL_AXI_CLK				9

#define VIDEO_CC_VENUS_CTL_CORE_CLK				10

#define VIDEO_CC_XO_CLK						11

#define VIDEO_CC_XO_CLK_SRC					12

#define VIDEO_PLL0_OUT_MAIN					0

#define VIDEO_CC_APB_CLK					1

#define VIDEO_CC_SLEEP_CLK					2

#define VIDEO_CC_SLEEP_CLK_SRC					3

#define VIDEO_CC_VCODEC0_AXI_CLK				4

#define VIDEO_CC_VCODEC0_CORE_CLK				5

#define VIDEO_CC_VENUS_AHB_CLK					6

#define VIDEO_CC_VENUS_CLK_SRC					7

#define VIDEO_CC_VENUS_CTL_AXI_CLK				8

#define VIDEO_CC_VENUS_CTL_CORE_CLK				9

#define VIDEO_CC_XO_CLK						10

#define VIDEO_CC_XO_CLK_SRC					11



#endif