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Commit 43f993a7 authored by Channagoud Kadabi's avatar Channagoud Kadabi Committed by Prasad Sodagudi
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ARM: dts: msm: Add LLCC device for SDM855 



LLCC (Last Level Cache Controller) is a additional cache memory in the
system added to reduce the memory access latency. This block also
provides debug functionalities to trace the ECC (Error Correction Code)
and AMON (Activity Monitor) to track the deadlock inside of LLCC
channels. Add device tree nodes for all of the LLCC blocks.

Change-Id: I8ff269d3c1da342754680639ccabbd57c8271a86
Signed-off-by: default avatarChannagoud Kadabi <ckadabi@codeaurora.org>
Signed-off-by: default avatarRunmin Wang <runminw@codeaurora.org>
parent a006512d

arch/arm64/boot/dts/qcom/sdm855.dtsi

+25 −0
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ 
#include <dt-bindings/clock/qcom,npucc-sdm855.h>

#include <dt-bindings/clock/qcom,rpmh.h>

#include <dt-bindings/clock/qcom,aop-qmp.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>



/ {

	model = "Qualcomm Technologies, Inc. SDM855";
@@ -546,6 +547,30 @@ 
				  "l3-scu-faultirq";

	};



	qcom,llcc@9200000 {

		compatible = "qcom,llcc-core", "syscon", "simple-mfd";

		reg = <0x9200000 0x450000>;

		reg-names = "llcc_base";

		qcom,llcc-banks-off = <0x0 0x80000 0x100000 0x180000>;

		qcom,llcc-broadcast-off = <0x400000>;



		llcc: qcom,sdm855-llcc {

			compatible = "qcom,sdm855-llcc";

			#cache-cells = <1>;

			max-slices = <32>;

		};



		qcom,llcc-erp {

			compatible = "qcom,llcc-erp";

			interrupt-names = "ecc_irq";

			interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;

		};



		qcom,llcc-amon {

			compatible = "qcom,llcc-amon";

		};

	};



	usb0: ssusb@a600000 {

		compatible = "qcom,dwc3";

		reg = <0x0a600000 0x100000>;