crypto: rockchip - add crypto driver for rk3288 (433cd2c6) · Commits · e / devices / android_kernel_oneplus_sm8150

drivers/crypto/Kconfig

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		@@ -497,4 +497,15 @@ config CRYPTO_DEV_SUN4I_SS
		To compile this driver as a module, choose M here: the module
		will be called sun4i-ss.

		config CRYPTO_DEV_ROCKCHIP
		tristate "Rockchip's Cryptographic Engine driver"
		depends on OF && ARCH_ROCKCHIP
		select CRYPTO_AES
		select CRYPTO_DES
		select CRYPTO_BLKCIPHER

		help
		This driver interfaces with the hardware crypto accelerator.
		Supporting cbc/ecb chainmode, and aes/des/des3_ede cipher mode.

		endif # CRYPTO_HW

drivers/crypto/Makefile

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Original line number	Diff line number	Diff line
		@@ -29,3 +29,4 @@ obj-$(CONFIG_CRYPTO_DEV_QAT) += qat/
		obj-$(CONFIG_CRYPTO_DEV_QCE) += qce/
		obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/
		obj-$(CONFIG_CRYPTO_DEV_SUN4I_SS) += sunxi-ss/
		obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP) += rockchip/

drivers/crypto/rockchip/Makefile

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Original line number	Diff line number	Diff line
		obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP) += rk_crypto.o
		rk_crypto-objs := rk3288_crypto.o \
		rk3288_crypto_ablkcipher.o \

drivers/crypto/rockchip/rk3288_crypto.c

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Original line number	Diff line number	Diff line
		/*
		* Crypto acceleration support for Rockchip RK3288
		*
		* Copyright (c) 2015, Fuzhou Rockchip Electronics Co., Ltd
		*
		* Author: Zain Wang <zain.wang@rock-chips.com>
		*
		* This program is free software; you can redistribute it and/or modify it
		* under the terms and conditions of the GNU General Public License,
		* version 2, as published by the Free Software Foundation.
		*
		* Some ideas are from marvell-cesa.c and s5p-sss.c driver.
		*/

		#include "rk3288_crypto.h"
		#include <linux/module.h>
		#include <linux/platform_device.h>
		#include <linux/of.h>
		#include <linux/clk.h>
		#include <linux/crypto.h>
		#include <linux/reset.h>

		static int rk_crypto_enable_clk(struct rk_crypto_info *dev)
		{
		int err;

		err = clk_prepare_enable(dev->sclk);
		if (err) {
		dev_err(dev->dev, "[%s:%d], Couldn't enable clock sclk\n",
		__func__, __LINE__);
		goto err_return;
		}
		err = clk_prepare_enable(dev->aclk);
		if (err) {
		dev_err(dev->dev, "[%s:%d], Couldn't enable clock aclk\n",
		__func__, __LINE__);
		goto err_aclk;
		}
		err = clk_prepare_enable(dev->hclk);
		if (err) {
		dev_err(dev->dev, "[%s:%d], Couldn't enable clock hclk\n",
		__func__, __LINE__);
		goto err_hclk;
		}
		err = clk_prepare_enable(dev->dmaclk);
		if (err) {
		dev_err(dev->dev, "[%s:%d], Couldn't enable clock dmaclk\n",
		__func__, __LINE__);
		goto err_dmaclk;
		}
		return err;
		err_dmaclk:
		clk_disable_unprepare(dev->hclk);
		err_hclk:
		clk_disable_unprepare(dev->aclk);
		err_aclk:
		clk_disable_unprepare(dev->sclk);
		err_return:
		return err;
		}

		static void rk_crypto_disable_clk(struct rk_crypto_info *dev)
		{
		clk_disable_unprepare(dev->dmaclk);
		clk_disable_unprepare(dev->hclk);
		clk_disable_unprepare(dev->aclk);
		clk_disable_unprepare(dev->sclk);
		}

		static int check_alignment(struct scatterlist *sg_src,
		struct scatterlist *sg_dst,
		int align_mask)
		{
		int in, out, align;

		in = IS_ALIGNED((uint32_t)sg_src->offset, 4) &&
		IS_ALIGNED((uint32_t)sg_src->length, align_mask);
		if (!sg_dst)
		return in;
		out = IS_ALIGNED((uint32_t)sg_dst->offset, 4) &&
		IS_ALIGNED((uint32_t)sg_dst->length, align_mask);
		align = in && out;

		return (align && (sg_src->length == sg_dst->length));
		}

		static int rk_load_data(struct rk_crypto_info *dev,
		struct scatterlist *sg_src,
		struct scatterlist *sg_dst)
		{
		unsigned int count;

		dev->aligned = dev->aligned ?
		check_alignment(sg_src, sg_dst, dev->align_size) :
		dev->aligned;
		if (dev->aligned) {
		count = min(dev->left_bytes, sg_src->length);
		dev->left_bytes -= count;

		if (!dma_map_sg(dev->dev, sg_src, 1, DMA_TO_DEVICE)) {
		dev_err(dev->dev, "[%s:%d] dma_map_sg(src) error\n",
		__func__, __LINE__);
		return -EINVAL;
		}
		dev->addr_in = sg_dma_address(sg_src);

		if (sg_dst) {
		if (!dma_map_sg(dev->dev, sg_dst, 1, DMA_FROM_DEVICE)) {
		dev_err(dev->dev,
		"[%s:%d] dma_map_sg(dst) error\n",
		__func__, __LINE__);
		dma_unmap_sg(dev->dev, sg_src, 1,
		DMA_TO_DEVICE);
		return -EINVAL;
		}
		dev->addr_out = sg_dma_address(sg_dst);
		}
		} else {
		count = (dev->left_bytes > PAGE_SIZE) ?
		PAGE_SIZE : dev->left_bytes;

		if (!sg_pcopy_to_buffer(dev->first, dev->nents,
		dev->addr_vir, count,
		dev->total - dev->left_bytes)) {
		dev_err(dev->dev, "[%s:%d] pcopy err\n",
		__func__, __LINE__);
		return -EINVAL;
		}
		dev->left_bytes -= count;
		sg_init_one(&dev->sg_tmp, dev->addr_vir, count);
		if (!dma_map_sg(dev->dev, &dev->sg_tmp, 1, DMA_TO_DEVICE)) {
		dev_err(dev->dev, "[%s:%d] dma_map_sg(sg_tmp) error\n",
		__func__, __LINE__);
		return -ENOMEM;
		}
		dev->addr_in = sg_dma_address(&dev->sg_tmp);

		if (sg_dst) {
		if (!dma_map_sg(dev->dev, &dev->sg_tmp, 1,
		DMA_FROM_DEVICE)) {
		dev_err(dev->dev,
		"[%s:%d] dma_map_sg(sg_tmp) error\n",
		__func__, __LINE__);
		dma_unmap_sg(dev->dev, &dev->sg_tmp, 1,
		DMA_TO_DEVICE);
		return -ENOMEM;
		}
		dev->addr_out = sg_dma_address(&dev->sg_tmp);
		}
		}
		dev->count = count;
		return 0;
		}

		static void rk_unload_data(struct rk_crypto_info *dev)
		{
		struct scatterlist sg_in, sg_out;

		sg_in = dev->aligned ? dev->sg_src : &dev->sg_tmp;
		dma_unmap_sg(dev->dev, sg_in, 1, DMA_TO_DEVICE);

		if (dev->sg_dst) {
		sg_out = dev->aligned ? dev->sg_dst : &dev->sg_tmp;
		dma_unmap_sg(dev->dev, sg_out, 1, DMA_FROM_DEVICE);
		}
		}

		static irqreturn_t rk_crypto_irq_handle(int irq, void *dev_id)
		{
		struct rk_crypto_info *dev = platform_get_drvdata(dev_id);
		u32 interrupt_status;
		int err = 0;

		spin_lock(&dev->lock);
		interrupt_status = CRYPTO_READ(dev, RK_CRYPTO_INTSTS);
		CRYPTO_WRITE(dev, RK_CRYPTO_INTSTS, interrupt_status);
		if (interrupt_status & 0x0a) {
		dev_warn(dev->dev, "DMA Error\n");
		err = -EFAULT;
		} else if (interrupt_status & 0x05) {
		err = dev->update(dev);
		}
		if (err)
		dev->complete(dev, err);
		spin_unlock(&dev->lock);
		return IRQ_HANDLED;
		}

		static void rk_crypto_tasklet_cb(unsigned long data)
		{
		struct rk_crypto_info dev = (struct rk_crypto_info )data;
		struct crypto_async_request async_req, backlog;
		int err = 0;

		spin_lock(&dev->lock);
		backlog = crypto_get_backlog(&dev->queue);
		async_req = crypto_dequeue_request(&dev->queue);
		spin_unlock(&dev->lock);
		if (!async_req) {
		dev_err(dev->dev, "async_req is NULL !!\n");
		return;
		}
		if (backlog) {
		backlog->complete(backlog, -EINPROGRESS);
		backlog = NULL;
		}

		if (crypto_tfm_alg_type(async_req->tfm) == CRYPTO_ALG_TYPE_ABLKCIPHER)
		dev->ablk_req = ablkcipher_request_cast(async_req);
		err = dev->start(dev);
		if (err)
		dev->complete(dev, err);
		}

		static struct rk_crypto_tmp *rk_cipher_algs[] = {
		&rk_ecb_aes_alg,
		&rk_cbc_aes_alg,
		&rk_ecb_des_alg,
		&rk_cbc_des_alg,
		&rk_ecb_des3_ede_alg,
		&rk_cbc_des3_ede_alg,
		};

		static int rk_crypto_register(struct rk_crypto_info *crypto_info)
		{
		unsigned int i, k;
		int err = 0;

		for (i = 0; i < ARRAY_SIZE(rk_cipher_algs); i++) {
		rk_cipher_algs[i]->dev = crypto_info;
		err = crypto_register_alg(&rk_cipher_algs[i]->alg);
		if (err)
		goto err_cipher_algs;
		}
		return 0;

		err_cipher_algs:
		for (k = 0; k < i; k++)
		crypto_unregister_alg(&rk_cipher_algs[k]->alg);
		return err;
		}

		static void rk_crypto_unregister(void)
		{
		unsigned int i;

		for (i = 0; i < ARRAY_SIZE(rk_cipher_algs); i++)
		crypto_unregister_alg(&rk_cipher_algs[i]->alg);
		}

		static void rk_crypto_action(void *data)
		{
		struct rk_crypto_info *crypto_info = data;

		reset_control_assert(crypto_info->rst);
		}

		static const struct of_device_id crypto_of_id_table[] = {
		{ .compatible = "rockchip,rk3288-crypto" },
		{}
		};
		MODULE_DEVICE_TABLE(of, crypto_of_id_table);

		static int rk_crypto_probe(struct platform_device *pdev)
		{
		struct resource *res;
		struct device *dev = &pdev->dev;
		struct rk_crypto_info *crypto_info;
		int err = 0;

		crypto_info = devm_kzalloc(&pdev->dev,
		sizeof(*crypto_info), GFP_KERNEL);
		if (!crypto_info) {
		err = -ENOMEM;
		goto err_crypto;
		}

		crypto_info->rst = devm_reset_control_get(dev, "crypto-rst");
		if (IS_ERR(crypto_info->rst)) {
		err = PTR_ERR(crypto_info->rst);
		goto err_crypto;
		}

		reset_control_assert(crypto_info->rst);
		usleep_range(10, 20);
		reset_control_deassert(crypto_info->rst);

		err = devm_add_action(dev, rk_crypto_action, crypto_info);
		if (err) {
		reset_control_assert(crypto_info->rst);
		goto err_crypto;
		}

		spin_lock_init(&crypto_info->lock);

		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
		crypto_info->reg = devm_ioremap_resource(&pdev->dev, res);
		if (IS_ERR(crypto_info->reg)) {
		err = PTR_ERR(crypto_info->reg);
		goto err_crypto;
		}

		crypto_info->aclk = devm_clk_get(&pdev->dev, "aclk");
		if (IS_ERR(crypto_info->aclk)) {
		err = PTR_ERR(crypto_info->aclk);
		goto err_crypto;
		}

		crypto_info->hclk = devm_clk_get(&pdev->dev, "hclk");
		if (IS_ERR(crypto_info->hclk)) {
		err = PTR_ERR(crypto_info->hclk);
		goto err_crypto;
		}

		crypto_info->sclk = devm_clk_get(&pdev->dev, "sclk");
		if (IS_ERR(crypto_info->sclk)) {
		err = PTR_ERR(crypto_info->sclk);
		goto err_crypto;
		}

		crypto_info->dmaclk = devm_clk_get(&pdev->dev, "apb_pclk");
		if (IS_ERR(crypto_info->dmaclk)) {
		err = PTR_ERR(crypto_info->dmaclk);
		goto err_crypto;
		}

		crypto_info->irq = platform_get_irq(pdev, 0);
		if (crypto_info->irq < 0) {
		dev_warn(crypto_info->dev,
		"control Interrupt is not available.\n");
		err = crypto_info->irq;
		goto err_crypto;
		}

		err = devm_request_irq(&pdev->dev, crypto_info->irq,
		rk_crypto_irq_handle, IRQF_SHARED,
		"rk-crypto", pdev);

		if (err) {
		dev_err(crypto_info->dev, "irq request failed.\n");
		goto err_crypto;
		}

		crypto_info->dev = &pdev->dev;
		platform_set_drvdata(pdev, crypto_info);

		tasklet_init(&crypto_info->crypto_tasklet,
		rk_crypto_tasklet_cb, (unsigned long)crypto_info);
		crypto_init_queue(&crypto_info->queue, 50);

		crypto_info->enable_clk = rk_crypto_enable_clk;
		crypto_info->disable_clk = rk_crypto_disable_clk;
		crypto_info->load_data = rk_load_data;
		crypto_info->unload_data = rk_unload_data;

		err = rk_crypto_register(crypto_info);
		if (err) {
		dev_err(dev, "err in register alg");
		goto err_register_alg;
		}

		dev_info(dev, "Crypto Accelerator successfully registered\n");
		return 0;

		err_register_alg:
		tasklet_kill(&crypto_info->crypto_tasklet);
		err_crypto:
		return err;
		}

		static int rk_crypto_remove(struct platform_device *pdev)
		{
		struct rk_crypto_info *crypto_tmp = platform_get_drvdata(pdev);

		rk_crypto_unregister();
		tasklet_kill(&crypto_tmp->crypto_tasklet);
		return 0;
		}

		static struct platform_driver crypto_driver = {
		.probe = rk_crypto_probe,
		.remove = rk_crypto_remove,
		.driver = {
		.name = "rk3288-crypto",
		.of_match_table = crypto_of_id_table,
		},
		};

		module_platform_driver(crypto_driver);

		MODULE_AUTHOR("Zain Wang <zain.wang@rock-chips.com>");
		MODULE_DESCRIPTION("Support for Rockchip's cryptographic engine");
		MODULE_LICENSE("GPL");

drivers/crypto/rockchip/rk3288_crypto.h

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Original line number	Diff line number	Diff line
		#ifndef __RK3288_CRYPTO_H__
		#define __RK3288_CRYPTO_H__

		#include <crypto/aes.h>
		#include <crypto/des.h>
		#include <crypto/algapi.h>
		#include <linux/interrupt.h>
		#include <linux/delay.h>

		#define _SBF(v, f) ((v) << (f))

		/* Crypto control registers*/
		#define RK_CRYPTO_INTSTS 0x0000
		#define RK_CRYPTO_PKA_DONE_INT BIT(5)
		#define RK_CRYPTO_HASH_DONE_INT BIT(4)
		#define RK_CRYPTO_HRDMA_ERR_INT BIT(3)
		#define RK_CRYPTO_HRDMA_DONE_INT BIT(2)
		#define RK_CRYPTO_BCDMA_ERR_INT BIT(1)
		#define RK_CRYPTO_BCDMA_DONE_INT BIT(0)

		#define RK_CRYPTO_INTENA 0x0004
		#define RK_CRYPTO_PKA_DONE_ENA BIT(5)
		#define RK_CRYPTO_HASH_DONE_ENA BIT(4)
		#define RK_CRYPTO_HRDMA_ERR_ENA BIT(3)
		#define RK_CRYPTO_HRDMA_DONE_ENA BIT(2)
		#define RK_CRYPTO_BCDMA_ERR_ENA BIT(1)
		#define RK_CRYPTO_BCDMA_DONE_ENA BIT(0)

		#define RK_CRYPTO_CTRL 0x0008
		#define RK_CRYPTO_WRITE_MASK _SBF(0xFFFF, 16)
		#define RK_CRYPTO_TRNG_FLUSH BIT(9)
		#define RK_CRYPTO_TRNG_START BIT(8)
		#define RK_CRYPTO_PKA_FLUSH BIT(7)
		#define RK_CRYPTO_HASH_FLUSH BIT(6)
		#define RK_CRYPTO_BLOCK_FLUSH BIT(5)
		#define RK_CRYPTO_PKA_START BIT(4)
		#define RK_CRYPTO_HASH_START BIT(3)
		#define RK_CRYPTO_BLOCK_START BIT(2)
		#define RK_CRYPTO_TDES_START BIT(1)
		#define RK_CRYPTO_AES_START BIT(0)

		#define RK_CRYPTO_CONF 0x000c
		/* HASH Receive DMA Address Mode: fix \| increment */
		#define RK_CRYPTO_HR_ADDR_MODE BIT(8)
		/* Block Transmit DMA Address Mode: fix \| increment */
		#define RK_CRYPTO_BT_ADDR_MODE BIT(7)
		/* Block Receive DMA Address Mode: fix \| increment */
		#define RK_CRYPTO_BR_ADDR_MODE BIT(6)
		#define RK_CRYPTO_BYTESWAP_HRFIFO BIT(5)
		#define RK_CRYPTO_BYTESWAP_BTFIFO BIT(4)
		#define RK_CRYPTO_BYTESWAP_BRFIFO BIT(3)
		/* AES = 0 OR DES = 1 */
		#define RK_CRYPTO_DESSEL BIT(2)
		#define RK_CYYPTO_HASHINSEL_INDEPENDENT_SOURCE _SBF(0x00, 0)
		#define RK_CYYPTO_HASHINSEL_BLOCK_CIPHER_INPUT _SBF(0x01, 0)
		#define RK_CYYPTO_HASHINSEL_BLOCK_CIPHER_OUTPUT _SBF(0x02, 0)

		/* Block Receiving DMA Start Address Register */
		#define RK_CRYPTO_BRDMAS 0x0010
		/* Block Transmitting DMA Start Address Register */
		#define RK_CRYPTO_BTDMAS 0x0014
		/* Block Receiving DMA Length Register */
		#define RK_CRYPTO_BRDMAL 0x0018
		/* Hash Receiving DMA Start Address Register */
		#define RK_CRYPTO_HRDMAS 0x001c
		/* Hash Receiving DMA Length Register */
		#define RK_CRYPTO_HRDMAL 0x0020

		/* AES registers */
		#define RK_CRYPTO_AES_CTRL 0x0080
		#define RK_CRYPTO_AES_BYTESWAP_CNT BIT(11)
		#define RK_CRYPTO_AES_BYTESWAP_KEY BIT(10)
		#define RK_CRYPTO_AES_BYTESWAP_IV BIT(9)
		#define RK_CRYPTO_AES_BYTESWAP_DO BIT(8)
		#define RK_CRYPTO_AES_BYTESWAP_DI BIT(7)
		#define RK_CRYPTO_AES_KEY_CHANGE BIT(6)
		#define RK_CRYPTO_AES_ECB_MODE _SBF(0x00, 4)
		#define RK_CRYPTO_AES_CBC_MODE _SBF(0x01, 4)
		#define RK_CRYPTO_AES_CTR_MODE _SBF(0x02, 4)
		#define RK_CRYPTO_AES_128BIT_key _SBF(0x00, 2)
		#define RK_CRYPTO_AES_192BIT_key _SBF(0x01, 2)
		#define RK_CRYPTO_AES_256BIT_key _SBF(0x02, 2)
		/* Slave = 0 / fifo = 1 */
		#define RK_CRYPTO_AES_FIFO_MODE BIT(1)
		/* Encryption = 0 , Decryption = 1 */
		#define RK_CRYPTO_AES_DEC BIT(0)

		#define RK_CRYPTO_AES_STS 0x0084
		#define RK_CRYPTO_AES_DONE BIT(0)

		/* AES Input Data 0-3 Register */
		#define RK_CRYPTO_AES_DIN_0 0x0088
		#define RK_CRYPTO_AES_DIN_1 0x008c
		#define RK_CRYPTO_AES_DIN_2 0x0090
		#define RK_CRYPTO_AES_DIN_3 0x0094

		/* AES output Data 0-3 Register */
		#define RK_CRYPTO_AES_DOUT_0 0x0098
		#define RK_CRYPTO_AES_DOUT_1 0x009c
		#define RK_CRYPTO_AES_DOUT_2 0x00a0
		#define RK_CRYPTO_AES_DOUT_3 0x00a4

		/* AES IV Data 0-3 Register */
		#define RK_CRYPTO_AES_IV_0 0x00a8
		#define RK_CRYPTO_AES_IV_1 0x00ac
		#define RK_CRYPTO_AES_IV_2 0x00b0
		#define RK_CRYPTO_AES_IV_3 0x00b4

		/* AES Key Data 0-3 Register */
		#define RK_CRYPTO_AES_KEY_0 0x00b8
		#define RK_CRYPTO_AES_KEY_1 0x00bc
		#define RK_CRYPTO_AES_KEY_2 0x00c0
		#define RK_CRYPTO_AES_KEY_3 0x00c4
		#define RK_CRYPTO_AES_KEY_4 0x00c8
		#define RK_CRYPTO_AES_KEY_5 0x00cc
		#define RK_CRYPTO_AES_KEY_6 0x00d0
		#define RK_CRYPTO_AES_KEY_7 0x00d4

		/* des/tdes */
		#define RK_CRYPTO_TDES_CTRL 0x0100
		#define RK_CRYPTO_TDES_BYTESWAP_KEY BIT(8)
		#define RK_CRYPTO_TDES_BYTESWAP_IV BIT(7)
		#define RK_CRYPTO_TDES_BYTESWAP_DO BIT(6)
		#define RK_CRYPTO_TDES_BYTESWAP_DI BIT(5)
		/* 0: ECB, 1: CBC */
		#define RK_CRYPTO_TDES_CHAINMODE_CBC BIT(4)
		/* TDES Key Mode, 0 : EDE, 1 : EEE */
		#define RK_CRYPTO_TDES_EEE BIT(3)
		/* 0: DES, 1:TDES */
		#define RK_CRYPTO_TDES_SELECT BIT(2)
		/* 0: Slave, 1:Fifo */
		#define RK_CRYPTO_TDES_FIFO_MODE BIT(1)
		/* Encryption = 0 , Decryption = 1 */
		#define RK_CRYPTO_TDES_DEC BIT(0)

		#define RK_CRYPTO_TDES_STS 0x0104
		#define RK_CRYPTO_TDES_DONE BIT(0)

		#define RK_CRYPTO_TDES_DIN_0 0x0108
		#define RK_CRYPTO_TDES_DIN_1 0x010c
		#define RK_CRYPTO_TDES_DOUT_0 0x0110
		#define RK_CRYPTO_TDES_DOUT_1 0x0114
		#define RK_CRYPTO_TDES_IV_0 0x0118
		#define RK_CRYPTO_TDES_IV_1 0x011c
		#define RK_CRYPTO_TDES_KEY1_0 0x0120
		#define RK_CRYPTO_TDES_KEY1_1 0x0124
		#define RK_CRYPTO_TDES_KEY2_0 0x0128
		#define RK_CRYPTO_TDES_KEY2_1 0x012c
		#define RK_CRYPTO_TDES_KEY3_0 0x0130
		#define RK_CRYPTO_TDES_KEY3_1 0x0134

		#define CRYPTO_READ(dev, offset) \
		readl_relaxed(((dev)->reg + (offset)))
		#define CRYPTO_WRITE(dev, offset, val) \
		writel_relaxed((val), ((dev)->reg + (offset)))

		struct rk_crypto_info {
		struct device *dev;
		struct clk *aclk;
		struct clk *hclk;
		struct clk *sclk;
		struct clk *dmaclk;
		struct reset_control *rst;
		void __iomem *reg;
		int irq;
		struct crypto_queue queue;
		struct tasklet_struct crypto_tasklet;
		struct ablkcipher_request *ablk_req;
		/* device lock */
		spinlock_t lock;

		/* the public variable */
		struct scatterlist *sg_src;
		struct scatterlist *sg_dst;
		struct scatterlist sg_tmp;
		struct scatterlist *first;
		unsigned int left_bytes;
		void *addr_vir;
		int aligned;
		int align_size;
		size_t nents;
		unsigned int total;
		unsigned int count;
		u32 mode;
		dma_addr_t addr_in;
		dma_addr_t addr_out;
		int (start)(struct rk_crypto_info dev);
		int (update)(struct rk_crypto_info dev);
		void (complete)(struct rk_crypto_info dev, int err);
		int (enable_clk)(struct rk_crypto_info dev);
		void (disable_clk)(struct rk_crypto_info dev);
		int (load_data)(struct rk_crypto_info dev,
		struct scatterlist *sg_src,
		struct scatterlist *sg_dst);
		void (unload_data)(struct rk_crypto_info dev);
		};

		/* the private variable of cipher */
		struct rk_cipher_ctx {
		struct rk_crypto_info *dev;
		unsigned int keylen;
		};

		struct rk_crypto_tmp {
		struct rk_crypto_info *dev;
		struct crypto_alg alg;
		};

		extern struct rk_crypto_tmp rk_ecb_aes_alg;
		extern struct rk_crypto_tmp rk_cbc_aes_alg;
		extern struct rk_crypto_tmp rk_ecb_des_alg;
		extern struct rk_crypto_tmp rk_cbc_des_alg;
		extern struct rk_crypto_tmp rk_ecb_des3_ede_alg;
		extern struct rk_crypto_tmp rk_cbc_des3_ede_alg;

		#endif