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Commit 42ed458a authored by Stephane Eranian's avatar Stephane Eranian Committed by Andi Kleen
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[PATCH] i386: i386 add X86_FEATURE_PEBS and detection 



Here is a patch (used by perfmon2) to detect the presence of the Precise Event
Based Sampling (PEBS) feature for i386.  The patch also adds the cpu_has_pebs
macro.

- adds X86_FEATURE_PEBS

- adds cpu_has_pebs to test for X86_FEATURE_PEBS

Signed-off-by: default avatarstephane eranian <eranian@hpl.hp.com>
Signed-off-by: default avatarAndi Kleen <ak@suse.de>
Cc: Andi Kleen <ak@suse.de>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
parent d7731c0f

arch/i386/kernel/cpu/intel.c

+7 −1
Original line number Original line Diff line number Diff line
@@ -195,8 +195,14 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c) 
	if ((c->x86 == 0xf && c->x86_model >= 0x03) ||

	if ((c->x86 == 0xf && c->x86_model >= 0x03) ||

		(c->x86 == 0x6 && c->x86_model >= 0x0e))

		(c->x86 == 0x6 && c->x86_model >= 0x0e))

		set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);

		set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);

}





	if (cpu_has_ds) {

		unsigned int l1;

		rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);

		if (!(l1 & (1<<12)))

			set_bit(X86_FEATURE_PEBS, c->x86_capability);

	}

}





static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 * c, unsigned int size)

static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 * c, unsigned int size)

{

{

include/asm-i386/cpufeature.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -73,6 +73,7 @@ 
#define X86_FEATURE_UP		(3*32+ 9) /* smp kernel running on up */

#define X86_FEATURE_UP		(3*32+ 9) /* smp kernel running on up */

#define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* FXSAVE leaks FOP/FIP/FOP */

#define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* FXSAVE leaks FOP/FIP/FOP */

#define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */

#define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */

#define X86_FEATURE_PEBS	(3*32+12)  /* Precise-Event Based Sampling */





/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */

/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */

#define X86_FEATURE_XMM3	(4*32+ 0) /* Streaming SIMD Extensions-3 */

#define X86_FEATURE_XMM3	(4*32+ 0) /* Streaming SIMD Extensions-3 */
@@ -135,6 +136,7 @@ 
#define cpu_has_pmm		boot_cpu_has(X86_FEATURE_PMM)

#define cpu_has_pmm		boot_cpu_has(X86_FEATURE_PMM)

#define cpu_has_pmm_enabled	boot_cpu_has(X86_FEATURE_PMM_EN)

#define cpu_has_pmm_enabled	boot_cpu_has(X86_FEATURE_PMM_EN)

#define cpu_has_ds		boot_cpu_has(X86_FEATURE_DS)

#define cpu_has_ds		boot_cpu_has(X86_FEATURE_DS)

#define cpu_has_pebs 		boot_cpu_has(X86_FEATURE_PEBS)





#endif /* __ASM_I386_CPUFEATURE_H */

#endif /* __ASM_I386_CPUFEATURE_H */