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Commit 42bc6748 authored by Dhaval Patel's avatar Dhaval Patel Committed by Steve Cohen
Browse files

drm/msm: send "set0 tcs" command for wake and sleep tcs 



Send "set0 tcs" command for wake and sleep tcs to avoid
tcs send hang during mode-2 exit. This is done based
on RSCC hardware sequence update to avoid any TCS send
hang.

Change-Id: I988966eff6892f762aa11d67d2cadb993fbed7c9
Signed-off-by: default avatarDhaval Patel <pdhaval@codeaurora.org>
parent 14c384f4

drivers/gpu/drm/msm/sde_rsc_hw.c

+4 −4
Original line number Diff line number Diff line
@@ -204,17 +204,17 @@ static int rsc_hw_seq_memory_init(struct sde_rsc_priv *rsc) 


	/* tcs sleep & wake sequence */

	dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_MEM_0_DRV0 + 0x2c,

						0x2089e6a6, rsc->debug_mode);

						0x89e686a6, rsc->debug_mode);

	dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_MEM_0_DRV0 + 0x30,

						0xe7a7e9a9, rsc->debug_mode);

						0xa7e9a920, rsc->debug_mode);

	dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_MEM_0_DRV0 + 0x34,

						0x00002089, rsc->debug_mode);

						0x2089e787, rsc->debug_mode);



	/* branch address */

	dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_CFG_BR_ADDR_0_DRV0,

						0x2a, rsc->debug_mode);

	dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_CFG_BR_ADDR_1_DRV0,

						0x30, rsc->debug_mode);

						0x31, rsc->debug_mode);



	return 0;

}