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Commit 424b6898 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 

Pull clk fixes from Stephen Boyd:
 "A handful of Sunxi and Rockchip clk driver fixes and a core framework
  one where we need to copy a string because we can't guarantee it isn't
  freed sometime later"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: sunxi-ng: fix recalc_rate formula of NKMP clocks
  clk: sunxi-ng: Fix div/mult settings for osc12M on A64
  clk: rockchip: Make uartpll a child of the gpll on rk3036
  clk: rockchip: add "," to mux_pll_src_apll_dpll_gpll_usb480m_p on rk3036
  clk: core: Copy connection id
  dt-bindings: arm: update Armada CP110 system controller binding
  clk: sunxi-ng: sun6i: Fix enable bit offset for hdmi-ddc module clock
  clk: sunxi: ccu-sun5i needs nkmp
  clk: sunxi-ng: mp: Adjust parent rate for pre-dividers
parents d07c6f46 7f0b97d5

Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt

+3 −3
Original line number Original line Diff line number Diff line
@@ -45,7 +45,7 @@ The following clocks are available: 
   - 1 15	SATA

   - 1 15	SATA

   - 1 16	SATA USB

   - 1 16	SATA USB

   - 1 17	Main

   - 1 17	Main

   - 1 18	SD/MMC

   - 1 18	SD/MMC/GOP

   - 1 21	Slow IO (SPI, NOR, BootROM, I2C, UART)

   - 1 21	Slow IO (SPI, NOR, BootROM, I2C, UART)

   - 1 22	USB3H0

   - 1 22	USB3H0

   - 1 23	USB3H1

   - 1 23	USB3H1
@@ -65,7 +65,7 @@ Required properties: 
	"cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",

	"cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",

	"cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",

	"cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",

	"cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",

	"cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",

	"cpm-sata-usb", "cpm-main", "cpm-sd-mmc", "none", "none", "cpm-slow-io",

	"cpm-sata-usb", "cpm-main", "cpm-sd-mmc-gop", "none", "none", "cpm-slow-io",

	"cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";

	"cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";





Example:

Example:
@@ -78,6 +78,6 @@ Example: 
		gate-clock-output-names = "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",

		gate-clock-output-names = "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",

			"cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",

			"cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",

			"cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",

			"cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",

			"cpm-sata-usb", "cpm-main", "cpm-sd-mmc", "none", "none", "cpm-slow-io",

			"cpm-sata-usb", "cpm-main", "cpm-sd-mmc-gop", "none", "none", "cpm-slow-io",

			"cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";

			"cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";

	};
 
	};

drivers/clk/clk.c

+2 −1
Original line number Original line Diff line number Diff line
@@ -2502,7 +2502,7 @@ struct clk *__clk_create_clk(struct clk_hw *hw, const char *dev_id, 




	clk->core = hw->core;

	clk->core = hw->core;

	clk->dev_id = dev_id;

	clk->dev_id = dev_id;

	clk->con_id = con_id;

	clk->con_id = kstrdup_const(con_id, GFP_KERNEL);

	clk->max_rate = ULONG_MAX;

	clk->max_rate = ULONG_MAX;





	clk_prepare_lock();

	clk_prepare_lock();
@@ -2518,6 +2518,7 @@ void __clk_free_clk(struct clk *clk) 
	hlist_del(&clk->clks_node);

	hlist_del(&clk->clks_node);

	clk_prepare_unlock();

	clk_prepare_unlock();





	kfree_const(clk->con_id);

	kfree(clk);

	kfree(clk);

}

}

drivers/clk/rockchip/clk-rk3036.c

+8 −1
Original line number Original line Diff line number Diff line
@@ -127,7 +127,7 @@ PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" }; 
PNAME(mux_pll_src_3plls_p)	= { "apll", "dpll", "gpll" };

PNAME(mux_pll_src_3plls_p)	= { "apll", "dpll", "gpll" };

PNAME(mux_timer_p)		= { "xin24m", "pclk_peri_src" };

PNAME(mux_timer_p)		= { "xin24m", "pclk_peri_src" };





PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p)	= { "apll", "dpll", "gpll" "usb480m" };

PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p)	= { "apll", "dpll", "gpll", "usb480m" };





PNAME(mux_mmc_src_p)	= { "apll", "dpll", "gpll", "xin24m" };

PNAME(mux_mmc_src_p)	= { "apll", "dpll", "gpll", "xin24m" };

PNAME(mux_i2s_pre_p)	= { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };

PNAME(mux_i2s_pre_p)	= { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
@@ -450,6 +450,13 @@ static void __init rk3036_clk_init(struct device_node *np) 
		return;

		return;

	}

	}





	/*

	 * Make uart_pll_clk a child of the gpll, as all other sources are

	 * not that usable / stable.

	 */

	writel_relaxed(HIWORD_UPDATE(0x2, 0x3, 10),

		       reg_base + RK2928_CLKSEL_CON(13));



	ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);

	ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);

	if (IS_ERR(ctx)) {

	if (IS_ERR(ctx)) {

		pr_err("%s: rockchip clk init failed\n", __func__);

		pr_err("%s: rockchip clk init failed\n", __func__);

drivers/clk/sunxi-ng/Kconfig

+1 −0
Original line number Original line Diff line number Diff line
@@ -80,6 +80,7 @@ config SUN6I_A31_CCU 
	select SUNXI_CCU_DIV

	select SUNXI_CCU_DIV

	select SUNXI_CCU_NK

	select SUNXI_CCU_NK

	select SUNXI_CCU_NKM

	select SUNXI_CCU_NKM

	select SUNXI_CCU_NKMP

	select SUNXI_CCU_NM

	select SUNXI_CCU_NM

	select SUNXI_CCU_MP

	select SUNXI_CCU_MP

	select SUNXI_CCU_PHASE

	select SUNXI_CCU_PHASE

drivers/clk/sunxi-ng/ccu-sun50i-a64.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -566,7 +566,7 @@ static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu", 
			     0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);

			     0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);





/* Fixed Factor clocks */

/* Fixed Factor clocks */

static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 1, 2, 0);

static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 2, 1, 0);





/* We hardcode the divider to 4 for now */

/* We hardcode the divider to 4 for now */

static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",

static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",