i7core_edac: CodingStyle fixes (41fcb7fe) · Commits · e / devices / android_kernel_oneplus_sm8150

drivers/edac/i7core_edac.c

+32 −27

Original line number	Original line	Diff line number	Diff line
	@@ -352,9 +352,8 @@ static int i7core_get_active_channels(int channels, int csrows)
	continue;		continue;

	/* Check if the channel is disabled */		/* Check if the channel is disabled */
	if (status & (1 << i)) {		if (status & (1 << i))
	continue;		continue;
	}

	pdev = get_pdev_slot_func(i + 4, 1);		pdev = get_pdev_slot_func(i + 4, 1);
	if (!pdev) {		if (!pdev) {
	@@ -550,9 +549,9 @@ static int get_dimm_config(struct mem_ctl_info *mci)
	pci_read_config_dword(pdev, MC_SAG_CH_5, &value[5]);		pci_read_config_dword(pdev, MC_SAG_CH_5, &value[5]);
	pci_read_config_dword(pdev, MC_SAG_CH_6, &value[6]);		pci_read_config_dword(pdev, MC_SAG_CH_6, &value[6]);
	pci_read_config_dword(pdev, MC_SAG_CH_7, &value[7]);		pci_read_config_dword(pdev, MC_SAG_CH_7, &value[7]);
	printk("\t[%i] DIVBY3\tREMOVED\tOFFSET\n", i);		debugf0("\t[%i] DIVBY3\tREMOVED\tOFFSET\n", i);
	for (j = 0; j < 8; j++)		for (j = 0; j < 8; j++)
	printk("\t\t%#x\t%#x\t%#x\n",		debugf0("\t\t%#x\t%#x\t%#x\n",
	(value[j] >> 27) & 0x1,		(value[j] >> 27) & 0x1,
	(value[j] >> 24) & 0x7,		(value[j] >> 24) & 0x7,
	(value[j] && ((1 << 24) - 1)));		(value[j] && ((1 << 24) - 1)));
	@@ -923,7 +922,8 @@ static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci,
	pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],		pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
	MC_CHANNEL_ERROR_MASK, injectmask);		MC_CHANNEL_ERROR_MASK, injectmask);

	debugf0("Error inject addr match 0x%016llx, ecc 0x%08x, inject 0x%08x\n",		debugf0("Error inject addr match 0x%016llx, ecc 0x%08x,"
			" inject 0x%08x\n",
	mask, pvt->inject.eccmask, injectmask);		mask, pvt->inject.eccmask, injectmask);


	@@ -1249,7 +1249,12 @@ static int __devinit i7core_probe(struct pci_dev *pdev,
	memset(pvt, 0, sizeof(*pvt));		memset(pvt, 0, sizeof(*pvt));

	mci->mc_idx = 0;		mci->mc_idx = 0;
	mci->mtype_cap = MEM_FLAG_DDR3; /* FIXME: how to handle RDDR3? */		/*
			* FIXME: how to handle RDDR3 at MCI level? It is possible to have
			* Mixed RDDR3/UDDR3 with Nehalem, provided that they are on different
			* memory channels
			*/
			mci->mtype_cap = MEM_FLAG_DDR3;
	mci->edac_ctl_cap = EDAC_FLAG_NONE;		mci->edac_ctl_cap = EDAC_FLAG_NONE;
	mci->edac_cap = EDAC_FLAG_NONE;		mci->edac_cap = EDAC_FLAG_NONE;
	mci->mod_name = "i7core_edac.c";		mci->mod_name = "i7core_edac.c";