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Commit 41e8c70e authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'bcm7278' 



Florian Fainelli says:

====================
net: dsa: bcm_sf2: Add support for BCM7278

This patch series adds support for the Broadcom BCM7278 integrated switch
which is a successor of the BCM7445 switch. We have a little bit of
register shuffling going on, which is why most of the functional changes
are to deal with that.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents b20b564b 039a7b85

Documentation/devicetree/bindings/net/brcm,bcm7445-switch-v4.0.txt

+9 −1
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 


Required properties:



- compatible: should be "brcm,bcm7445-switch-v4.0"

- compatible: should be "brcm,bcm7445-switch-v4.0" or "brcm,bcm7278-switch-v4.0"

- reg: addresses and length of the register sets for the device, must be 6

  pairs of register addresses and lengths

- interrupts: interrupts for the devices, must be two interrupts
@@ -41,6 +41,13 @@ Optional properties: 
  Admission Control Block supports reporting the number of packets in-flight in a

  switch queue



Port subnodes:



Optional properties:



- brcm,use-bcm-hdr: boolean property, if present, indicates that the switch

  port has Broadcom tags enabled (per-packet metadata)



Example:



switch_top@f0b00000 {
@@ -114,6 +121,7 @@ switch_top@f0b00000 { 
			port@0 {

				label = "gphy";

				reg = <0>;

				brcm,use-bcm-hdr;

			};

			...

		};

drivers/net/dsa/b53/b53_common.c

+12 −0
Original line number Diff line number Diff line
@@ -1685,6 +1685,18 @@ static const struct b53_chip_data b53_switch_chips[] = { 
		.jumbo_pm_reg = B53_JUMBO_PORT_MASK,

		.jumbo_size_reg = B53_JUMBO_MAX_SIZE,

	},

	{

		.chip_id = BCM7278_DEVICE_ID,

		.dev_name = "BCM7278",

		.vlans = 4096,

		.enabled_ports = 0x1ff,

		.arl_entries= 4,

		.cpu_port = B53_CPU_PORT,

		.vta_regs = B53_VTA_REGS,

		.duplex_reg = B53_DUPLEX_STAT_GE,

		.jumbo_pm_reg = B53_JUMBO_PORT_MASK,

		.jumbo_size_reg = B53_JUMBO_MAX_SIZE,

	},

};



static int b53_switch_init(struct b53_device *dev)

drivers/net/dsa/b53/b53_priv.h

+3 −1
Original line number Diff line number Diff line
@@ -62,6 +62,7 @@ enum { 
	BCM53019_DEVICE_ID = 0x53019,

	BCM58XX_DEVICE_ID = 0x5800,

	BCM7445_DEVICE_ID = 0x7445,

	BCM7278_DEVICE_ID = 0x7278,

};



#define B53_N_PORTS	9
@@ -179,7 +180,8 @@ static inline int is5301x(struct b53_device *dev) 
static inline int is58xx(struct b53_device *dev)

{

	return dev->chip_id == BCM58XX_DEVICE_ID ||

		dev->chip_id == BCM7445_DEVICE_ID;

		dev->chip_id == BCM7445_DEVICE_ID ||

		dev->chip_id == BCM7278_DEVICE_ID;

}



#define B53_CPU_PORT_25	5

drivers/net/dsa/bcm_sf2.c

+133 −34
Original line number Diff line number Diff line
@@ -61,30 +61,10 @@ static void bcm_sf2_imp_vlan_setup(struct dsa_switch *ds, int cpu_port) 
	}

}



static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)

static void bcm_sf2_brcm_hdr_setup(struct bcm_sf2_priv *priv, int port)

{

	struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);

	u32 reg, val;



	/* Enable the port memories */

	reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);

	reg &= ~P_TXQ_PSM_VDD(port);

	core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);



	/* Enable Broadcast, Multicast, Unicast forwarding to IMP port */

	reg = core_readl(priv, CORE_IMP_CTL);

	reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);

	reg &= ~(RX_DIS | TX_DIS);

	core_writel(priv, reg, CORE_IMP_CTL);



	/* Enable forwarding */

	core_writel(priv, SW_FWDG_EN, CORE_SWMODE);



	/* Enable IMP port in dumb mode */

	reg = core_readl(priv, CORE_SWITCH_CTRL);

	reg |= MII_DUMB_FWDG_EN;

	core_writel(priv, reg, CORE_SWITCH_CTRL);



	/* Resolve which bit controls the Broadcom tag */

	switch (port) {

	case 8:
@@ -119,11 +99,43 @@ static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port) 
	reg = core_readl(priv, CORE_BRCM_HDR_TX_DIS);

	reg &= ~(1 << port);

	core_writel(priv, reg, CORE_BRCM_HDR_TX_DIS);

}



static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)

{

	struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);

	u32 reg, offset;



	if (priv->type == BCM7445_DEVICE_ID)

		offset = CORE_STS_OVERRIDE_IMP;

	else

		offset = CORE_STS_OVERRIDE_IMP2;



	/* Enable the port memories */

	reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);

	reg &= ~P_TXQ_PSM_VDD(port);

	core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);



	/* Enable Broadcast, Multicast, Unicast forwarding to IMP port */

	reg = core_readl(priv, CORE_IMP_CTL);

	reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);

	reg &= ~(RX_DIS | TX_DIS);

	core_writel(priv, reg, CORE_IMP_CTL);



	/* Enable forwarding */

	core_writel(priv, SW_FWDG_EN, CORE_SWMODE);



	/* Enable IMP port in dumb mode */

	reg = core_readl(priv, CORE_SWITCH_CTRL);

	reg |= MII_DUMB_FWDG_EN;

	core_writel(priv, reg, CORE_SWITCH_CTRL);



	bcm_sf2_brcm_hdr_setup(priv, port);



	/* Force link status for IMP port */

	reg = core_readl(priv, CORE_STS_OVERRIDE_IMP);

	reg = core_readl(priv, offset);

	reg |= (MII_SW_OR | LINK_STS);

	core_writel(priv, reg, CORE_STS_OVERRIDE_IMP);

	core_writel(priv, reg, offset);

}



static void bcm_sf2_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
@@ -224,6 +236,10 @@ static int bcm_sf2_port_setup(struct dsa_switch *ds, int port, 
	reg &= ~P_TXQ_PSM_VDD(port);

	core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);



	/* Enable Broadcom tags for that port if requested */

	if (priv->brcm_tag_mask & BIT(port))

		bcm_sf2_brcm_hdr_setup(priv, port);



	/* Clear the Rx and Tx disable bits and set to no spanning tree */

	core_writel(priv, 0, CORE_G_PCTL_PORT(port));
@@ -503,6 +519,9 @@ static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv, 


		if (mode == PHY_INTERFACE_MODE_MOCA)

			priv->moca_port = port_num;



		if (of_property_read_bool(port, "brcm,use-bcm-hdr"))

			priv->brcm_tag_mask |= 1 << port_num;

	}

}
@@ -591,7 +610,12 @@ static void bcm_sf2_sw_adjust_link(struct dsa_switch *ds, int port, 
	struct ethtool_eee *p = &priv->port_sts[port].eee;

	u32 id_mode_dis = 0, port_mode;

	const char *str = NULL;

	u32 reg;

	u32 reg, offset;



	if (priv->type == BCM7445_DEVICE_ID)

		offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);

	else

		offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);



	switch (phydev->interface) {

	case PHY_INTERFACE_MODE_RGMII:
@@ -662,7 +686,7 @@ static void bcm_sf2_sw_adjust_link(struct dsa_switch *ds, int port, 
	if (phydev->duplex == DUPLEX_FULL)

		reg |= DUPLX_MODE;



	core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port));

	core_writel(priv, reg, offset);



	if (!phydev->is_pseudo_fixed_link)

		p->eee_enabled = bcm_sf2_eee_init(ds, port, phydev);
@@ -672,9 +696,14 @@ static void bcm_sf2_sw_fixed_link_update(struct dsa_switch *ds, int port, 
					 struct fixed_phy_status *status)

{

	struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);

	u32 duplex, pause;

	u32 duplex, pause, offset;

	u32 reg;



	if (priv->type == BCM7445_DEVICE_ID)

		offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);

	else

		offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);



	duplex = core_readl(priv, CORE_DUPSTS);

	pause = core_readl(priv, CORE_PAUSESTS);
@@ -703,13 +732,13 @@ static void bcm_sf2_sw_fixed_link_update(struct dsa_switch *ds, int port, 
		status->duplex = !!(duplex & (1 << port));

	}



	reg = core_readl(priv, CORE_STS_OVERRIDE_GMIIP_PORT(port));

	reg = core_readl(priv, offset);

	reg |= SW_OVERRIDE;

	if (status->link)

		reg |= LINK_STS;

	else

		reg &= ~LINK_STS;

	core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port));

	core_writel(priv, reg, offset);



	if ((pause & (1 << port)) &&

	    (pause & (1 << (port + PAUSESTS_TX_PAUSE_SHIFT)))) {
@@ -1009,10 +1038,74 @@ static const struct dsa_switch_ops bcm_sf2_ops = { 
	.port_fdb_del		= b53_fdb_del,

};



struct bcm_sf2_of_data {

	u32 type;

	const u16 *reg_offsets;

	unsigned int core_reg_align;

};



/* Register offsets for the SWITCH_REG_* block */

static const u16 bcm_sf2_7445_reg_offsets[] = {

	[REG_SWITCH_CNTRL]	= 0x00,

	[REG_SWITCH_STATUS]	= 0x04,

	[REG_DIR_DATA_WRITE]	= 0x08,

	[REG_DIR_DATA_READ]	= 0x0C,

	[REG_SWITCH_REVISION]	= 0x18,

	[REG_PHY_REVISION]	= 0x1C,

	[REG_SPHY_CNTRL]	= 0x2C,

	[REG_RGMII_0_CNTRL]	= 0x34,

	[REG_RGMII_1_CNTRL]	= 0x40,

	[REG_RGMII_2_CNTRL]	= 0x4c,

	[REG_LED_0_CNTRL]	= 0x90,

	[REG_LED_1_CNTRL]	= 0x94,

	[REG_LED_2_CNTRL]	= 0x98,

};



static const struct bcm_sf2_of_data bcm_sf2_7445_data = {

	.type		= BCM7445_DEVICE_ID,

	.core_reg_align	= 0,

	.reg_offsets	= bcm_sf2_7445_reg_offsets,

};



static const u16 bcm_sf2_7278_reg_offsets[] = {

	[REG_SWITCH_CNTRL]	= 0x00,

	[REG_SWITCH_STATUS]	= 0x04,

	[REG_DIR_DATA_WRITE]	= 0x08,

	[REG_DIR_DATA_READ]	= 0x0c,

	[REG_SWITCH_REVISION]	= 0x10,

	[REG_PHY_REVISION]	= 0x14,

	[REG_SPHY_CNTRL]	= 0x24,

	[REG_RGMII_0_CNTRL]	= 0xe0,

	[REG_RGMII_1_CNTRL]	= 0xec,

	[REG_RGMII_2_CNTRL]	= 0xf8,

	[REG_LED_0_CNTRL]	= 0x40,

	[REG_LED_1_CNTRL]	= 0x4c,

	[REG_LED_2_CNTRL]	= 0x58,

};



static const struct bcm_sf2_of_data bcm_sf2_7278_data = {

	.type		= BCM7278_DEVICE_ID,

	.core_reg_align	= 1,

	.reg_offsets	= bcm_sf2_7278_reg_offsets,

};



static const struct of_device_id bcm_sf2_of_match[] = {

	{ .compatible = "brcm,bcm7445-switch-v4.0",

	  .data = &bcm_sf2_7445_data

	},

	{ .compatible = "brcm,bcm7278-switch-v4.0",

	  .data = &bcm_sf2_7278_data

	},

	{ /* sentinel */ },

};

MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);



static int bcm_sf2_sw_probe(struct platform_device *pdev)

{

	const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;

	struct device_node *dn = pdev->dev.of_node;

	const struct of_device_id *of_id = NULL;

	const struct bcm_sf2_of_data *data;

	struct b53_platform_data *pdata;

	struct dsa_switch_ops *ops;

	struct bcm_sf2_priv *priv;
@@ -1040,11 +1133,22 @@ static int bcm_sf2_sw_probe(struct platform_device *pdev) 
	if (!pdata)

		return -ENOMEM;



	of_id = of_match_node(bcm_sf2_of_match, dn);

	if (!of_id || !of_id->data)

		return -EINVAL;



	data = of_id->data;



	/* Set SWITCH_REG register offsets and SWITCH_CORE align factor */

	priv->type = data->type;

	priv->reg_offsets = data->reg_offsets;

	priv->core_reg_align = data->core_reg_align;



	/* Auto-detection using standard registers will not work, so

	 * provide an indication of what kind of device we are for

	 * b53_common to work with

	 */

	pdata->chip_id = BCM7445_DEVICE_ID;

	pdata->chip_id = priv->type;

	dev->pdata = pdata;



	priv->dev = dev;
@@ -1190,11 +1294,6 @@ static int bcm_sf2_resume(struct device *dev) 
static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops,

			 bcm_sf2_suspend, bcm_sf2_resume);



static const struct of_device_id bcm_sf2_of_match[] = {

	{ .compatible = "brcm,bcm7445-switch-v4.0" },

	{ /* sentinel */ },

};

MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);



static struct platform_driver bcm_sf2_driver = {

	.probe	= bcm_sf2_sw_probe,

drivers/net/dsa/bcm_sf2.h

+37 −4
Original line number Diff line number Diff line
@@ -61,6 +61,11 @@ struct bcm_sf2_priv { 
	void __iomem			*fcb;

	void __iomem			*acb;



	/* Register offsets indirection tables */

	u32 				type;

	const u16			*reg_offsets;

	unsigned int			core_reg_align;



	/* spinlock protecting access to the indirect registers */

	spinlock_t			indir_lock;
@@ -95,6 +100,9 @@ struct bcm_sf2_priv { 
	struct device_node		*master_mii_dn;

	struct mii_bus			*slave_mii_bus;

	struct mii_bus			*master_mii_bus;



	/* Bitmask of ports needing BRCM tags */

	unsigned int			brcm_tag_mask;

};



static inline struct bcm_sf2_priv *bcm_sf2_to_priv(struct dsa_switch *ds)
@@ -104,6 +112,11 @@ static inline struct bcm_sf2_priv *bcm_sf2_to_priv(struct dsa_switch *ds) 
	return dev->priv;

}



static inline u32 bcm_sf2_mangle_addr(struct bcm_sf2_priv *priv, u32 off)

{

	return off << priv->core_reg_align;

}



#define SF2_IO_MACRO(name) \

static inline u32 name##_readl(struct bcm_sf2_priv *priv, u32 off)	\

{									\
@@ -125,7 +138,7 @@ static inline u64 name##_readq(struct bcm_sf2_priv *priv, u32 off) \ 
{									\

	u32 indir, dir;							\

	spin_lock(&priv->indir_lock);					\

	dir = __raw_readl(priv->name + off);				\

	dir = name##_readl(priv, off);					\

	indir = reg_readl(priv, REG_DIR_DATA_READ);			\

	spin_unlock(&priv->indir_lock);					\

	return (u64)indir << 32 | dir;					\
@@ -135,7 +148,7 @@ static inline void name##_writeq(struct bcm_sf2_priv *priv, u64 val, \ 
{									\

	spin_lock(&priv->indir_lock);					\

	reg_writel(priv, upper_32_bits(val), REG_DIR_DATA_WRITE);	\

	__raw_writel(lower_32_bits(val), priv->name + off);		\

	name##_writel(priv, lower_32_bits(val), off);			\

	spin_unlock(&priv->indir_lock);					\

}
@@ -153,8 +166,28 @@ static inline void intrl2_##which##_mask_set(struct bcm_sf2_priv *priv, \ 
	priv->irq##which##_mask |= (mask);				\

}									\



SF2_IO_MACRO(core);

SF2_IO_MACRO(reg);

static inline u32 core_readl(struct bcm_sf2_priv *priv, u32 off)

{

	u32 tmp = bcm_sf2_mangle_addr(priv, off);

	return __raw_readl(priv->core + tmp);

}



static inline void core_writel(struct bcm_sf2_priv *priv, u32 val, u32 off)

{

	u32 tmp = bcm_sf2_mangle_addr(priv, off);

	__raw_writel(val, priv->core + tmp);

}



static inline u32 reg_readl(struct bcm_sf2_priv *priv, u16 off)

{

	return __raw_readl(priv->reg + priv->reg_offsets[off]);

}



static inline void reg_writel(struct bcm_sf2_priv *priv, u32 val, u16 off)

{

	__raw_writel(val, priv->reg + priv->reg_offsets[off]);

}



SF2_IO64_MACRO(core);

SF2_IO_MACRO(intrl2_0);

SF2_IO_MACRO(intrl2_1);