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Commit 41bfab35 authored by Pei Zhang's avatar Pei Zhang Committed by Zhenyu Wang
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drm/i915/gvt: add some new MMIOs to cmd_access white list 



Guest is now acces some MMIOs (0x215c, RING_INSTPM) through command which
is not originally in gvt's white list. This cause huge error log printed in
gvt.
This patch addes these MMIOs to the white list.

V2. change the commit message content.
V3. remove duplicate defination of 0x20c0.
V4. refine code style.

Signed-off-by: default avatarPei Zhang <pei.zhang@intel.com>
Signed-off-by: default avatarWeinan Li <weinan.z.li@intel.com>
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
parent 8bcd7c18

drivers/gpu/drm/i915/gvt/handlers.c

+3 −2
Original line number Diff line number Diff line
@@ -1589,7 +1589,8 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) 
#undef RING_REG



	MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK, NULL, NULL);

	MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK, NULL, NULL);

	MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,

			NULL, NULL);

	MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,

			ring_timestamp_mmio_read, NULL);

	MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
@@ -2284,7 +2285,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) 
	MMIO_D(0x1a054, D_ALL);



	MMIO_D(0x44070, D_ALL);

	MMIO_D(0x215c, D_HSW_PLUS);

	MMIO_DFH(0x215c, D_HSW_PLUS, F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(0x2178, D_ALL, F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(0x217c, D_ALL, F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(0x12178, D_ALL, F_CMD_ACCESS, NULL, NULL);