Commit 4163f3a0 authored Jan 31, 2018 by Deepak Katragadda

clk: qcom: gcc-sdm855: Change the halt_check flag for some GCC GPU clocks



The gcc_ddrss_gpu_axi_clk and gcc_gpu_memnoc_gfx_clk clocks are
controllable from the GPU SMMU clock voting registers. This might
lead them to remain enabled even after removing the SW vote on the
CBCRs. Update the halt_check flags for these clocks to BRANCH_VOTED
in order to only poll these CBCRs while enabling them.

Change-Id: Ie98ddef82e964b41af223267edc5380675d5b89f
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>

parent 2e6001c5

drivers/clk/qcom/gcc-sdm855.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -1955,7 +1955,7 @@ static struct clk_branch gcc_cpuss_rbcpr_clk = {

		static struct clk_branch gcc_ddrss_gpu_axi_clk = {
		.halt_reg = 0x71154,
		.halt_check = BRANCH_HALT,
		.halt_check = BRANCH_VOTED,
		.clkr = {
		.enable_reg = 0x71154,
		.enable_mask = BIT(0),
		@@ -2205,7 +2205,7 @@ static struct clk_branch gcc_gpu_iref_clk = {

		static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
		.halt_reg = 0x7100c,
		.halt_check = BRANCH_HALT,
		.halt_check = BRANCH_VOTED,
		.clkr = {
		.enable_reg = 0x7100c,
		.enable_mask = BIT(0),