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Commit 40bacf16 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
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drm/radeon/kms: add support for hw i2c on r1xx-r5xx 



wire hw i2c support into radeon i2c algo.

fixes merged:
- handle bus probing correctly
- use meaningful error numbers
- abort if transaction fails
- The line mapping is different depending on the asic.
- protect hw i2c engine with a mutex
- rs300 doesn't have a pin select bit
- r200 has a different pin select setup

Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 5a6f98f5

drivers/gpu/drm/radeon/r500_reg.h

+54 −46
Original line number Diff line number Diff line
@@ -717,54 +717,62 @@ 
#define AVIVO_DVOA_BIT_DEPTH_CONTROL			0x7988



#define AVIVO_DC_GPIO_HPD_A                 0x7e94



#define AVIVO_GPIO_0                        0x7e30

#define AVIVO_GPIO_1                        0x7e40

#define AVIVO_GPIO_2                        0x7e50

#define AVIVO_GPIO_3                        0x7e60



#define AVIVO_DC_GPIO_HPD_Y                 0x7e9c



#define AVIVO_I2C_STATUS					0x7d30

#	define AVIVO_I2C_STATUS_DONE				(1 << 0)

#	define AVIVO_I2C_STATUS_NACK				(1 << 1)

#	define AVIVO_I2C_STATUS_HALT				(1 << 2)

#	define AVIVO_I2C_STATUS_GO				(1 << 3)

#	define AVIVO_I2C_STATUS_MASK				0x7

/* If radeon_mm_i2c is to be believed, this is HALT, NACK, and maybe

 * DONE? */

#	define AVIVO_I2C_STATUS_CMD_RESET			0x7

#	define AVIVO_I2C_STATUS_CMD_WAIT			(1 << 3)

#define AVIVO_I2C_STOP						0x7d34

#define AVIVO_I2C_START_CNTL				0x7d38

#	define AVIVO_I2C_START						(1 << 8)

#	define AVIVO_I2C_CONNECTOR0					(0 << 16)

#	define AVIVO_I2C_CONNECTOR1					(1 << 16)

#define R520_I2C_START (1<<0)

#define R520_I2C_STOP (1<<1)

#define R520_I2C_RX (1<<2)

#define R520_I2C_EN (1<<8)

#define R520_I2C_DDC1 (0<<16)

#define R520_I2C_DDC2 (1<<16)

#define R520_I2C_DDC3 (2<<16)

#define R520_I2C_DDC_MASK (3<<16)

#define AVIVO_I2C_CONTROL2					0x7d3c

#	define AVIVO_I2C_7D3C_SIZE_SHIFT			8

#	define AVIVO_I2C_7D3C_SIZE_MASK				(0xf << 8)

#define AVIVO_I2C_CONTROL3						0x7d40

/* Reading is done 4 bytes at a time: read the bottom 8 bits from

 * 7d44, four times in a row.

 * Writing is a little more complex.  First write DATA with

 * 0xnnnnnnzz, then 0xnnnnnnyy, where nnnnnn is some non-deterministic

 * magic number, zz is, I think, the slave address, and yy is the byte

 * you want to write. */

#define AVIVO_I2C_DATA						0x7d44

#define R520_I2C_ADDR_COUNT_MASK (0x7)

#define R520_I2C_DATA_COUNT_SHIFT (8)

#define R520_I2C_DATA_COUNT_MASK (0xF00)

#define AVIVO_I2C_CNTL						0x7d50

#	define AVIVO_I2C_EN							(1 << 0)

#	define AVIVO_I2C_RESET						(1 << 8)

#define AVIVO_DC_I2C_STATUS1				0x7d30

#	define AVIVO_DC_I2C_DONE			(1 << 0)

#	define AVIVO_DC_I2C_NACK			(1 << 1)

#	define AVIVO_DC_I2C_HALT			(1 << 2)

#	define AVIVO_DC_I2C_GO			        (1 << 3)

#define AVIVO_DC_I2C_RESET 				0x7d34

#	define AVIVO_DC_I2C_SOFT_RESET			(1 << 0)

#	define AVIVO_DC_I2C_ABORT			(1 << 8)

#define AVIVO_DC_I2C_CONTROL1 				0x7d38

#	define AVIVO_DC_I2C_START			(1 << 0)

#	define AVIVO_DC_I2C_STOP			(1 << 1)

#	define AVIVO_DC_I2C_RECEIVE			(1 << 2)

#	define AVIVO_DC_I2C_EN			        (1 << 8)

#	define AVIVO_DC_I2C_PIN_SELECT(x)		((x) << 16)

#	define AVIVO_SEL_DDC1			        0

#	define AVIVO_SEL_DDC2			        1

#	define AVIVO_SEL_DDC3			        2

#define AVIVO_DC_I2C_CONTROL2 				0x7d3c

#	define AVIVO_DC_I2C_ADDR_COUNT(x)		((x) << 0)

#	define AVIVO_DC_I2C_DATA_COUNT(x)		((x) << 8)

#define AVIVO_DC_I2C_CONTROL3 				0x7d40

#	define AVIVO_DC_I2C_DATA_DRIVE_EN		(1 << 0)

#	define AVIVO_DC_I2C_DATA_DRIVE_SEL		(1 << 1)

#	define AVIVO_DC_I2C_CLK_DRIVE_EN		(1 << 7)

#	define AVIVO_DC_I2C_RD_INTRA_BYTE_DELAY(x)      ((x) << 8)

#	define AVIVO_DC_I2C_WR_INTRA_BYTE_DELAY(x)	((x) << 16)

#	define AVIVO_DC_I2C_TIME_LIMIT(x)		((x) << 24)

#define AVIVO_DC_I2C_DATA 				0x7d44

#define AVIVO_DC_I2C_INTERRUPT_CONTROL 			0x7d48

#	define AVIVO_DC_I2C_INTERRUPT_STATUS		(1 << 0)

#	define AVIVO_DC_I2C_INTERRUPT_AK		(1 << 8)

#	define AVIVO_DC_I2C_INTERRUPT_ENABLE		(1 << 16)

#define AVIVO_DC_I2C_ARBITRATION 			0x7d50

#	define AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C		(1 << 0)

#	define AVIVO_DC_I2C_SW_CAN_USE_I2C		(1 << 1)

#	define AVIVO_DC_I2C_SW_DONE_USING_I2C		(1 << 8)

#	define AVIVO_DC_I2C_HW_NEEDS_I2C		(1 << 9)

#	define AVIVO_DC_I2C_ABORT_HDCP_I2C		(1 << 16)

#	define AVIVO_DC_I2C_HW_USING_I2C		(1 << 17)



#define AVIVO_DC_GPIO_DDC1_MASK 		        0x7e40

#define AVIVO_DC_GPIO_DDC1_A 		                0x7e44

#define AVIVO_DC_GPIO_DDC1_EN 		                0x7e48

#define AVIVO_DC_GPIO_DDC1_Y 		                0x7e4c



#define AVIVO_DC_GPIO_DDC2_MASK 		        0x7e50

#define AVIVO_DC_GPIO_DDC2_A 		                0x7e54

#define AVIVO_DC_GPIO_DDC2_EN 		                0x7e58

#define AVIVO_DC_GPIO_DDC2_Y 		                0x7e5c



#define AVIVO_DC_GPIO_DDC3_MASK 		        0x7e60

#define AVIVO_DC_GPIO_DDC3_A 		                0x7e64

#define AVIVO_DC_GPIO_DDC3_EN 		                0x7e68

#define AVIVO_DC_GPIO_DDC3_Y 		                0x7e6c



#define AVIVO_DISP_INTERRUPT_STATUS                             0x7edc

#       define AVIVO_D1_VBLANK_INTERRUPT                        (1 << 4)

drivers/gpu/drm/radeon/radeon.h

+1 −0
Original line number Diff line number Diff line
@@ -829,6 +829,7 @@ struct radeon_device { 
	struct r600_ih ih; /* r6/700 interrupt ring */

	struct workqueue_struct *wq;

	struct work_struct hotplug_work;

	struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */



	/* audio stuff */

	struct timer_list	audio_timer;

drivers/gpu/drm/radeon/radeon_combios.c

+67 −4
Original line number Diff line number Diff line
@@ -486,9 +486,65 @@ static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rde 
		i2c.y_data_reg = ddc_line;

	}



	if (rdev->family < CHIP_R200)

	switch (rdev->family) {

	case CHIP_R100:

	case CHIP_RV100:

	case CHIP_RS100:

	case CHIP_RV200:

	case CHIP_RS200:

	case CHIP_RS300:

		switch (ddc_line) {

		case RADEON_GPIO_DVI_DDC:

			/* in theory this should be hw capable,

			 * but it doesn't seem to work

			 */

			i2c.hw_capable = false;

	else {

			break;

		default:

			i2c.hw_capable = false;

			break;

		}

		break;

	case CHIP_R200:

		switch (ddc_line) {

		case RADEON_GPIO_DVI_DDC:

		case RADEON_GPIO_MONID:

			i2c.hw_capable = true;

			break;

		default:

			i2c.hw_capable = false;

			break;

		}

		break;

	case CHIP_RV250:

	case CHIP_RV280:

		switch (ddc_line) {

		case RADEON_GPIO_VGA_DDC:

		case RADEON_GPIO_DVI_DDC:

		case RADEON_GPIO_CRT2_DDC:

			i2c.hw_capable = true;

			break;

		default:

			i2c.hw_capable = false;

			break;

		}

		break;

	case CHIP_R300:

	case CHIP_R350:

		switch (ddc_line) {

		case RADEON_GPIO_VGA_DDC:

		case RADEON_GPIO_DVI_DDC:

			i2c.hw_capable = true;

			break;

		default:

			i2c.hw_capable = false;

			break;

		}

		break;

	case CHIP_RV350:

	case CHIP_RV380:

	case CHIP_RS400:

	case CHIP_RS480:

		switch (ddc_line) {

		case RADEON_GPIO_VGA_DDC:

		case RADEON_GPIO_DVI_DDC:
@@ -504,6 +560,10 @@ static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rde 
			i2c.hw_capable = false;

			break;

		}

		break;

	default:

		i2c.hw_capable = false;

		break;

	}

	i2c.mm_i2c = false;

	i2c.i2c_id = 0;
@@ -1253,7 +1313,10 @@ bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder 
				tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");

				break;

			case DDC_LCD: /* MM i2c */

				DRM_ERROR("MM i2c requires hw i2c engine\n");

				i2c_bus.valid = true;

				i2c_bus.hw_capable = true;

				i2c_bus.mm_i2c = true;

				tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");

				break;

			default:

				DRM_ERROR("Unsupported gpio %d\n", gpio);

drivers/gpu/drm/radeon/radeon_device.c

+1 −0
Original line number Diff line number Diff line
@@ -638,6 +638,7 @@ int radeon_device_init(struct radeon_device *rdev, 
	mutex_init(&rdev->cs_mutex);

	mutex_init(&rdev->ib_pool.mutex);

	mutex_init(&rdev->cp.mutex);

	mutex_init(&rdev->dc_hw_i2c_mutex);

	if (rdev->family >= CHIP_R600)

		spin_lock_init(&rdev->ih.lock);

	mutex_init(&rdev->gem.mutex);

drivers/gpu/drm/radeon/radeon_i2c.c

+586 −11
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ 
#include "drmP.h"

#include "radeon_drm.h"

#include "radeon.h"

#include "atom.h"



/**

 * radeon_ddc_probe
@@ -71,13 +72,25 @@ static void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state) 
	 */

	if (rec->hw_capable) {

		if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) {

			if (rec->a_clk_reg == RADEON_GPIO_MONID) {

			u32 reg;



			if (rdev->family >= CHIP_RV350)

				reg = RADEON_GPIO_MONID;

			else if ((rdev->family == CHIP_R300) ||

				 (rdev->family == CHIP_R350))

				reg = RADEON_GPIO_DVI_DDC;

			else

				reg = RADEON_GPIO_CRT2_DDC;



			mutex_lock(&rdev->dc_hw_i2c_mutex);

			if (rec->a_clk_reg == reg) {

				WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |

							       R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1)));

			} else {

				WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |

							       R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)));

			}

			mutex_unlock(&rdev->dc_hw_i2c_mutex);

		}

	}
@@ -168,22 +181,584 @@ static void set_data(void *i2c_priv, int data) 
	WREG32(rec->en_data_reg, val);

}



static int radeon_i2c_xfer(struct i2c_adapter *i2c_adap,

/* hw i2c engine for r1xx-4xx hardware

 * hw can buffer up to 15 bytes

 */

static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap,

			    struct i2c_msg *msgs, int num)

{

	struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);

	struct radeon_device *rdev = i2c->dev->dev_private;

	struct radeon_i2c_bus_rec *rec = &i2c->rec;

	struct i2c_msg *p;

	int i, j, k, ret = num;

	/* XXX: use get_engine_clock() to get the current sclk */

	u32 prescale = (((rdev->clock.default_sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;

	u32 i2c_cntl_0, i2c_cntl_1, i2c_data;

	u32 tmp, reg;



	mutex_lock(&rdev->dc_hw_i2c_mutex);



	reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) |

	       RADEON_I2C_START |

	       RADEON_I2C_STOP |

	       RADEON_I2C_GO);



	if (rdev->is_atom_bios) {

		tmp = RREG32(RADEON_BIOS_6_SCRATCH);

		WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);

	}



	if (rec->mm_i2c) {

		i2c_cntl_0 = RADEON_I2C_CNTL_0;

		i2c_cntl_1 = RADEON_I2C_CNTL_1;

		i2c_data = RADEON_I2C_DATA;

	} else {

		i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0;

		i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1;

		i2c_data = RADEON_DVI_I2C_DATA;



		switch (rdev->family) {

		case CHIP_R100:

		case CHIP_RV100:

		case CHIP_RS100:

		case CHIP_RV200:

		case CHIP_RS200:

		case CHIP_RS300:

			switch (rec->mask_clk_reg) {

			case RADEON_GPIO_DVI_DDC:

				/* no gpio select bit */

				break;

			default:

				DRM_ERROR("gpio not supported with hw i2c\n");

				ret = -EINVAL;

				goto done;

			}

			break;

		case CHIP_R200:

			/* only bit 4 on r200 */

			switch (rec->mask_clk_reg) {

			case RADEON_GPIO_DVI_DDC:

				reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);

				break;

			case RADEON_GPIO_MONID:

				reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);

				break;

			default:

				DRM_ERROR("gpio not supported with hw i2c\n");

				ret = -EINVAL;

				goto done;

			}

			break;

		case CHIP_RV250:

		case CHIP_RV280:

			/* bits 3 and 4 */

			switch (rec->mask_clk_reg) {

			case RADEON_GPIO_DVI_DDC:

				reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);

				break;

			case RADEON_GPIO_VGA_DDC:

				reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);

				break;

			case RADEON_GPIO_CRT2_DDC:

				reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);

				break;

			default:

				DRM_ERROR("gpio not supported with hw i2c\n");

				ret = -EINVAL;

				goto done;

			}

			break;

		case CHIP_R300:

		case CHIP_R350:

			/* only bit 4 on r300/r350 */

			switch (rec->mask_clk_reg) {

			case RADEON_GPIO_VGA_DDC:

				reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);

				break;

			case RADEON_GPIO_DVI_DDC:

				reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);

				break;

			default:

				DRM_ERROR("gpio not supported with hw i2c\n");

				ret = -EINVAL;

				goto done;

			}

			break;

		case CHIP_RV350:

		case CHIP_RV380:

		case CHIP_R420:

		case CHIP_R423:

		case CHIP_RV410:

		case CHIP_RS400:

		case CHIP_RS480:

			/* bits 3 and 4 */

			switch (rec->mask_clk_reg) {

			case RADEON_GPIO_VGA_DDC:

				reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);

				break;

			case RADEON_GPIO_DVI_DDC:

				reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);

				break;

			case RADEON_GPIO_MONID:

				reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);

				break;

			default:

				DRM_ERROR("gpio not supported with hw i2c\n");

				ret = -EINVAL;

				goto done;

			}

			break;

		default:

			DRM_ERROR("unsupported asic\n");

			ret = -EINVAL;

			goto done;

			break;

		}

	}



	/* check for bus probe */

	p = &msgs[0];

	if ((num == 1) && (p->len == 0)) {

		WREG32(i2c_cntl_0, (RADEON_I2C_DONE |

				    RADEON_I2C_NACK |

				    RADEON_I2C_HALT |

				    RADEON_I2C_SOFT_RST));

		WREG32(i2c_data, (p->addr << 1) & 0xff);

		WREG32(i2c_data, 0);

		WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |

				    (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |

				    RADEON_I2C_EN |

				    (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));

		WREG32(i2c_cntl_0, reg);

		for (k = 0; k < 32; k++) {

			udelay(10);

			tmp = RREG32(i2c_cntl_0);

			if (tmp & RADEON_I2C_GO)

				continue;

			tmp = RREG32(i2c_cntl_0);

			if (tmp & RADEON_I2C_DONE)

				break;

			else {

				DRM_DEBUG("i2c write error 0x%08x\n", tmp);

				WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);

				ret = -EIO;

				goto done;

			}

		}

		goto done;

	}



	for (i = 0; i < num; i++) {

		p = &msgs[i];

		for (j = 0; j < p->len; j++) {

			if (p->flags & I2C_M_RD) {

				WREG32(i2c_cntl_0, (RADEON_I2C_DONE |

						    RADEON_I2C_NACK |

						    RADEON_I2C_HALT |

						    RADEON_I2C_SOFT_RST));

				WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1);

				WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |

						    (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |

						    RADEON_I2C_EN |

						    (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));

				WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE);

				for (k = 0; k < 32; k++) {

					udelay(10);

					tmp = RREG32(i2c_cntl_0);

					if (tmp & RADEON_I2C_GO)

						continue;

					tmp = RREG32(i2c_cntl_0);

					if (tmp & RADEON_I2C_DONE)

						break;

					else {

						DRM_DEBUG("i2c read error 0x%08x\n", tmp);

						WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);

						ret = -EIO;

						goto done;

					}

				}

				p->buf[j] = RREG32(i2c_data) & 0xff;

			} else {

				WREG32(i2c_cntl_0, (RADEON_I2C_DONE |

						    RADEON_I2C_NACK |

						    RADEON_I2C_HALT |

						    RADEON_I2C_SOFT_RST));

				WREG32(i2c_data, (p->addr << 1) & 0xff);

				WREG32(i2c_data, p->buf[j]);

				WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |

						    (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |

						    RADEON_I2C_EN |

						    (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));

				WREG32(i2c_cntl_0, reg);

				for (k = 0; k < 32; k++) {

					udelay(10);

					tmp = RREG32(i2c_cntl_0);

					if (tmp & RADEON_I2C_GO)

						continue;

					tmp = RREG32(i2c_cntl_0);

					if (tmp & RADEON_I2C_DONE)

						break;

					else {

						DRM_DEBUG("i2c write error 0x%08x\n", tmp);

						WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);

						ret = -EIO;

						goto done;

					}

				}

			}

		}

	}



done:

	WREG32(i2c_cntl_0, 0);

	WREG32(i2c_cntl_1, 0);

	WREG32(i2c_cntl_0, (RADEON_I2C_DONE |

			    RADEON_I2C_NACK |

			    RADEON_I2C_HALT |

			    RADEON_I2C_SOFT_RST));



	if (rdev->is_atom_bios) {

		tmp = RREG32(RADEON_BIOS_6_SCRATCH);

		tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;

		WREG32(RADEON_BIOS_6_SCRATCH, tmp);

	}



	mutex_unlock(&rdev->dc_hw_i2c_mutex);



	return ret;

}



/* hw i2c engine for r5xx hardware

 * hw can buffer up to 15 bytes

 */

static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap,

			    struct i2c_msg *msgs, int num)

{

	struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);

	struct radeon_device *rdev = i2c->dev->dev_private;

	struct radeon_i2c_bus_rec *rec = &i2c->rec;

	struct i2c_msg *p;

	int i2c_clock = 50;

	int i, j, remaining, current_count, buffer_offset, ret = num;

	/* XXX: use get_engine_clock() to get the current sclk */

	u32 prescale;

	u32 tmp, reg;

	u32 saved1, saved2;



	mutex_lock(&rdev->dc_hw_i2c_mutex);



	/* clear gpio mask bits */

	tmp = RREG32(rec->mask_clk_reg);

	tmp &= ~rec->mask_clk_mask;

	WREG32(rec->mask_clk_reg, tmp);

	tmp = RREG32(rec->mask_clk_reg);



	tmp = RREG32(rec->mask_data_reg);

	tmp &= ~rec->mask_data_mask;

	WREG32(rec->mask_data_reg, tmp);

	tmp = RREG32(rec->mask_data_reg);



	/* clear pin values */

	tmp = RREG32(rec->a_clk_reg);

	tmp &= ~rec->a_clk_mask;

	WREG32(rec->a_clk_reg, tmp);

	tmp = RREG32(rec->a_clk_reg);



	tmp = RREG32(rec->a_data_reg);

	tmp &= ~rec->a_data_mask;

	WREG32(rec->a_data_reg, tmp);

	tmp = RREG32(rec->a_data_reg);



	/* set the pins to input */

	tmp = RREG32(rec->en_clk_reg);

	tmp &= ~rec->en_clk_mask;

	WREG32(rec->en_clk_reg, tmp);

	tmp = RREG32(rec->en_clk_reg);



	tmp = RREG32(rec->en_data_reg);

	tmp &= ~rec->en_data_mask;

	WREG32(rec->en_data_reg, tmp);

	tmp = RREG32(rec->en_data_reg);



	/* */

	tmp = RREG32(RADEON_BIOS_6_SCRATCH);

	WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);

	saved1 = RREG32(AVIVO_DC_I2C_CONTROL1);

	saved2 = RREG32(0x494);

	WREG32(0x494, saved2 | 0x1);



	WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C);

	for (i = 0; i < 50; i++) {

		udelay(1);

		if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C)

			break;

	}

	if (i == 50) {

		DRM_ERROR("failed to get i2c bus\n");

		ret = -EBUSY;

		goto done;

	}



	if (rdev->family == CHIP_R520)

		prescale = (127 << 8) + ((rdev->clock.default_sclk * 10) / (4 * 127 * i2c_clock));

	else

		prescale = (((rdev->clock.default_sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;



	reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN;

	switch (rec->mask_clk_reg) {

	case AVIVO_DC_GPIO_DDC1_MASK:

		reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1);

		break;

	case AVIVO_DC_GPIO_DDC2_MASK:

		reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2);

		break;

	case AVIVO_DC_GPIO_DDC3_MASK:

		reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3);

		break;

	default:

		DRM_ERROR("gpio not supported with hw i2c\n");

		ret = -EINVAL;

		goto done;

	}



	/* check for bus probe */

	p = &msgs[0];

	if ((num == 1) && (p->len == 0)) {

		WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |

					      AVIVO_DC_I2C_NACK |

					      AVIVO_DC_I2C_HALT));

		WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);

		udelay(1);

		WREG32(AVIVO_DC_I2C_RESET, 0);



		WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);

		WREG32(AVIVO_DC_I2C_DATA, 0);



		WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));

		WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |

					       AVIVO_DC_I2C_DATA_COUNT(1) |

					       (prescale << 16)));

		WREG32(AVIVO_DC_I2C_CONTROL1, reg);

		WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);

		for (j = 0; j < 200; j++) {

			udelay(50);

			tmp = RREG32(AVIVO_DC_I2C_STATUS1);

			if (tmp & AVIVO_DC_I2C_GO)

				continue;

			tmp = RREG32(AVIVO_DC_I2C_STATUS1);

			if (tmp & AVIVO_DC_I2C_DONE)

				break;

			else {

				DRM_DEBUG("i2c write error 0x%08x\n", tmp);

				WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);

				ret = -EIO;

				goto done;

			}

		}

		goto done;

	}



	for (i = 0; i < num; i++) {

		p = &msgs[i];

		remaining = p->len;

		buffer_offset = 0;

		if (p->flags & I2C_M_RD) {

			while (remaining) {

				if (remaining > 15)

					current_count = 15;

				else

					current_count = remaining;

				WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |

							      AVIVO_DC_I2C_NACK |

							      AVIVO_DC_I2C_HALT));

				WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);

				udelay(1);

				WREG32(AVIVO_DC_I2C_RESET, 0);



				WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1);

				WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));

				WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |

							       AVIVO_DC_I2C_DATA_COUNT(current_count) |

							       (prescale << 16)));

				WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE);

				WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);

				for (j = 0; j < 200; j++) {

					udelay(50);

					tmp = RREG32(AVIVO_DC_I2C_STATUS1);

					if (tmp & AVIVO_DC_I2C_GO)

						continue;

					tmp = RREG32(AVIVO_DC_I2C_STATUS1);

					if (tmp & AVIVO_DC_I2C_DONE)

						break;

					else {

						DRM_DEBUG("i2c read error 0x%08x\n", tmp);

						WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);

						ret = -EIO;

						goto done;

					}

				}

				for (j = 0; j < current_count; j++)

					p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff;

				remaining -= current_count;

				buffer_offset += current_count;

			}

		} else {

			while (remaining) {

				if (remaining > 15)

					current_count = 15;

				else

					current_count = remaining;

				WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |

							      AVIVO_DC_I2C_NACK |

							      AVIVO_DC_I2C_HALT));

				WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);

				udelay(1);

				WREG32(AVIVO_DC_I2C_RESET, 0);



				WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);

				for (j = 0; j < current_count; j++)

					WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]);



				WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));

				WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |

							       AVIVO_DC_I2C_DATA_COUNT(current_count) |

							       (prescale << 16)));

				WREG32(AVIVO_DC_I2C_CONTROL1, reg);

				WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);

				for (j = 0; j < 200; j++) {

					udelay(50);

					tmp = RREG32(AVIVO_DC_I2C_STATUS1);

					if (tmp & AVIVO_DC_I2C_GO)

						continue;

					tmp = RREG32(AVIVO_DC_I2C_STATUS1);

					if (tmp & AVIVO_DC_I2C_DONE)

						break;

					else {

						DRM_DEBUG("i2c write error 0x%08x\n", tmp);

						WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);

						ret = -EIO;

						goto done;

					}

				}

				remaining -= current_count;

				buffer_offset += current_count;

			}

		}

	}



done:

	WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |

				      AVIVO_DC_I2C_NACK |

				      AVIVO_DC_I2C_HALT));

	WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);

	udelay(1);

	WREG32(AVIVO_DC_I2C_RESET, 0);



	WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C);

	WREG32(AVIVO_DC_I2C_CONTROL1, saved1);

	WREG32(0x494, saved2);

	tmp = RREG32(RADEON_BIOS_6_SCRATCH);

	tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;

	WREG32(RADEON_BIOS_6_SCRATCH, tmp);



	mutex_unlock(&rdev->dc_hw_i2c_mutex);



	return ret;

}



static int radeon_sw_i2c_xfer(struct i2c_adapter *i2c_adap,

			      struct i2c_msg *msgs, int num)

{

	struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);

	int ret;



	radeon_i2c_do_lock(i2c, 1);

	if (i2c_transfer(&i2c->algo.radeon.bit_adapter, msgs, num) == num)

		ret = num;

	else

		ret = -1;

	ret = i2c_transfer(&i2c->algo.radeon.bit_adapter, msgs, num);

	radeon_i2c_do_lock(i2c, 0);



	return ret;

}



static int radeon_i2c_xfer(struct i2c_adapter *i2c_adap,

			   struct i2c_msg *msgs, int num)

{

	struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);

	struct radeon_device *rdev = i2c->dev->dev_private;

	struct radeon_i2c_bus_rec *rec = &i2c->rec;

	int ret;



	switch (rdev->family) {

	case CHIP_R100:

	case CHIP_RV100:

	case CHIP_RS100:

	case CHIP_RV200:

	case CHIP_RS200:

	case CHIP_R200:

	case CHIP_RV250:

	case CHIP_RS300:

	case CHIP_RV280:

	case CHIP_R300:

	case CHIP_R350:

	case CHIP_RV350:

	case CHIP_RV380:

	case CHIP_R420:

	case CHIP_R423:

	case CHIP_RV410:

	case CHIP_RS400:

	case CHIP_RS480:

		if (rec->hw_capable)

			ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);

		else

			ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);

		break;

	case CHIP_RS600:

	case CHIP_RS690:

	case CHIP_RS740:

		/* XXX fill in hw i2c implementation */

		ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);

		break;

	case CHIP_RV515:

	case CHIP_R520:

	case CHIP_RV530:

	case CHIP_RV560:

	case CHIP_RV570:

	case CHIP_R580:

		if (rec->hw_capable) {

			if (rec->mm_i2c)

				ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);

			else

				ret = r500_hw_i2c_xfer(i2c_adap, msgs, num);

		} else

			ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);

		break;

	case CHIP_R600:

	case CHIP_RV610:

	case CHIP_RV630:

	case CHIP_RV670:

		/* XXX fill in hw i2c implementation */

		ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);

		break;

	case CHIP_RV620:

	case CHIP_RV635:

	case CHIP_RS780:

	case CHIP_RS880:

	case CHIP_RV770:

	case CHIP_RV730:

	case CHIP_RV710:

	case CHIP_RV740:

		/* XXX fill in hw i2c implementation */

		ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);

		break;

	default:

		DRM_ERROR("i2c: unhandled radeon chip\n");

		ret = -EIO;

		break;

	}



	return ret;

}



static u32 radeon_i2c_func(struct i2c_adapter *adap)

{

	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
@@ -205,8 +780,6 @@ struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 
	if (i2c == NULL)

		return NULL;



	i2c->dev = dev;

	i2c->rec = *rec;

	/* set the internal bit adapter */

	i2c->algo.radeon.bit_adapter.owner = THIS_MODULE;

	i2c_set_adapdata(&i2c->algo.radeon.bit_adapter, i2c);
@@ -223,10 +796,12 @@ struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 
	i2c->algo.radeon.bit_data.data = i2c;

	ret = i2c_bit_add_bus(&i2c->algo.radeon.bit_adapter);

	if (ret) {

		DRM_INFO("Failed to register internal bit i2c %s\n", name);

		DRM_ERROR("Failed to register internal bit i2c %s\n", name);

		goto out_free;

	}

	/* set the radeon i2c adapter */

	i2c->dev = dev;

	i2c->rec = *rec;

	i2c->adapter.owner = THIS_MODULE;

	i2c_set_adapdata(&i2c->adapter, i2c);

	sprintf(i2c->adapter.name, "Radeon i2c %s", name);
@@ -234,7 +809,7 @@ struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 
	i2c->adapter.algo = &radeon_i2c_algo;

	ret = i2c_add_adapter(&i2c->adapter);

	if (ret) {

		DRM_INFO("Failed to register i2c %s\n", name);

		DRM_ERROR("Failed to register i2c %s\n", name);

		goto out_free;

	}