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Commit 4031478a authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Disable usb host mode u1/u2 on SM8150"

parents dcd14f83 4844b025

arch/arm64/boot/dts/qcom/sm8150-usb.dtsi

+0 −1
Original line number Diff line number Diff line
@@ -84,7 +84,6 @@ 
			snps,disable-clk-gating;

			snps,has-lpm-erratum;

			snps,hird-threshold = /bits/ 8 <0x10>;

			snps,usb3_lpm_capable;

			snps,ssp-u3-u0-quirk;

			snps,usb3-u1u2-disable;

			usb-core-id = <0>;

drivers/usb/dwc3/core.c

+12 −0
Original line number Diff line number Diff line
@@ -846,6 +846,18 @@ int dwc3_core_init(struct dwc3 *dwc) 
		dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);

	}



	/*

	 * STAR: 9001346572:Host stops transfers to other EPs when a single

	 * USB2.0 EP NAKs continuously requires to disable internal retry

	 * feature

	 */

	if ((dwc->revision == DWC3_USB31_REVISION_170A) &&

		(dwc->versiontype == DWC3_USB31_VER_TYPE_GA)) {

		reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);

		reg |= DWC3_GUCTL3_USB20_RETRY_DISABLE;

		dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);

	}



	dwc3_notify_event(dwc, DWC3_CONTROLLER_POST_RESET_EVENT);



	return 0;

drivers/usb/dwc3/core.h

+5 −0
Original line number Diff line number Diff line
@@ -113,6 +113,7 @@ 
#define DWC3_GPRTBIMAP_FS0	0xc188

#define DWC3_GPRTBIMAP_FS1	0xc18c

#define DWC3_GUCTL2		0xc19c

#define DWC3_GUCTL3		0xc60c



#define DWC3_VER_NUMBER		0xc1a0

#define DWC3_VER_TYPE		0xc1a4
@@ -326,6 +327,9 @@ 
/* Global User Control Register 2 */

#define DWC3_GUCTL2_RST_ACTBITLATER		BIT(14)



/* Global User Control Register 3 */

#define DWC3_GUCTL3_USB20_RETRY_DISABLE		BIT(16)



/* Device Configuration Register */

#define DWC3_DCFG_DEVADDR(addr)	((addr) << 3)

#define DWC3_DCFG_DEVADDR_MASK	DWC3_DCFG_DEVADDR(0x7f)
@@ -1071,6 +1075,7 @@ struct dwc3 { 
	/* valid only for dwc31 configuraitons */

	u32			versiontype;

#define DWC3_USB31_VER_TYPE_EA06	0x65613036

#define DWC3_USB31_VER_TYPE_GA		0x67612a2a



	enum dwc3_ep0_next	ep0_next_event;

	enum dwc3_ep0_state	ep0state;