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Commit 4020ecff authored by Deepak Katragadda's avatar Deepak Katragadda
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clk: qcom: clk-cpu-osm: Correct the per_core_dcvs logic 



Information about whether per-core DCVS has been enabled for
a cluster is derived by checking whether the PER_CORE_DCVS_EN
bit is set. The current logic however checks if any bit of
the CORE_DCVS_CTRL register is set, and is thus wrong. Make
the correction.

Change-Id: Ia45e410f3ad8158dceffaa8741df659295675d4c
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent ef38a86a

drivers/clk/qcom/clk-cpu-osm.c

+2 −2
Original line number Diff line number Diff line
@@ -957,11 +957,11 @@ static int clk_cpu_osm_driver_probe(struct platform_device *pdev) 


	/* Check if per-core DCVS is enabled/not */

	val = clk_osm_read_reg(&pwrcl_clk, CORE_DCVS_CTRL);

	if (val && BIT(0))

	if (val & BIT(0))

		pwrcl_clk.per_core_dcvs = true;



	val = clk_osm_read_reg(&perfcl_clk, CORE_DCVS_CTRL);

	if (val && BIT(0))

	if (val & BIT(0))

		perfcl_clk.per_core_dcvs = true;



	rc = clk_osm_read_lut(pdev, &l3_clk);