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Commit 3fe5cadb authored by Giuseppe CAVALLARO's avatar Giuseppe CAVALLARO Committed by David S. Miller
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drivers: net: stmmac: rework core ISR to better manage PCS and PMT 



By default, all gmac cores disable the PCS block and always
enable the PMT.

Note that this is done in a different way by 3.x and 4.x cores.

With this rework, PCS and PMT interrupt masks can be driven by
parameters now moved inside the mac_device_info structure
and the settings follow what the HW capability register reports.

Signed-off-by: default avatarGiuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 70523e63

drivers/net/ethernet/stmicro/stmmac/common.h

+2 −0
Original line number Diff line number Diff line
@@ -529,6 +529,8 @@ struct mac_device_info { 
	int unicast_filter_entries;

	int mcast_bits_log2;

	unsigned int rx_csum;

	unsigned int pcs;

	unsigned int pmt;

};



struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr, int mcbins,

drivers/net/ethernet/stmicro/stmmac/dwmac1000.h

+20 −10
Original line number Diff line number Diff line
@@ -38,16 +38,26 @@ 
#define GMAC_WAKEUP_FILTER	0x00000028	/* Wake-up Frame Filter */



#define GMAC_INT_STATUS		0x00000038	/* interrupt status register */

enum dwmac1000_irq_status {

	lpiis_irq = 0x400,

	time_stamp_irq = 0x0200,

	mmc_rx_csum_offload_irq = 0x0080,

	mmc_tx_irq = 0x0040,

	mmc_rx_irq = 0x0020,

	mmc_irq = 0x0010,

	pmt_irq = 0x0008,

};

#define GMAC_INT_MASK		0x0000003c	/* interrupt mask register */

#define GMAC_INT_STATUS_PMT	BIT(3)

#define GMAC_INT_STATUS_MMCIS	BIT(4)

#define GMAC_INT_STATUS_MMCRIS	BIT(5)

#define GMAC_INT_STATUS_MMCTIS	BIT(6)

#define GMAC_INT_STATUS_MMCCSUM	BIT(7)

#define GMAC_INT_STATUS_TSTAMP	BIT(9)

#define GMAC_INT_STATUS_LPIIS	BIT(10)



/* interrupt mask register */

#define	GMAC_INT_MASK		0x0000003c

#define	GMAC_INT_DISABLE_RGMII		BIT(0)

#define	GMAC_INT_DISABLE_PCSLINK	BIT(1)

#define	GMAC_INT_DISABLE_PCSAN		BIT(2)

#define	GMAC_INT_DISABLE_PMT		BIT(3)

#define	GMAC_INT_DISABLE_TIMESTAMP	BIT(9)

#define	GMAC_INT_DISABLE_PCS	(GMAC_INT_DISABLE_RGMII | \

				 GMAC_INT_DISABLE_PCSLINK | \

				 GMAC_INT_DISABLE_PCSAN)

#define	GMAC_INT_DEFAULT_MASK	(GMAC_INT_DISABLE_TIMESTAMP | \

				 GMAC_INT_DISABLE_PCS)



/* PMT Control and Status */

#define GMAC_PMT		0x0000002c

drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c

+17 −7
Original line number Diff line number Diff line
@@ -37,7 +37,10 @@ static void dwmac1000_core_init(struct mac_device_info *hw, int mtu) 
{

	void __iomem *ioaddr = hw->pcsr;

	u32 value = readl(ioaddr + GMAC_CONTROL);



	/* Configure GMAC core */

	value |= GMAC_CORE_INIT;



	if (mtu > 1500)

		value |= GMAC_CONTROL_2K;

	if (mtu > 2000)
@@ -46,7 +49,14 @@ static void dwmac1000_core_init(struct mac_device_info *hw, int mtu) 
	writel(value, ioaddr + GMAC_CONTROL);



	/* Mask GMAC interrupts */

	writel(0x207, ioaddr + GMAC_INT_MASK);

	value = GMAC_INT_DEFAULT_MASK;



	if (hw->pmt)

		value &= ~GMAC_INT_DISABLE_PMT;

	if (hw->pcs)

		value &= ~GMAC_INT_DISABLE_PCS;



	writel(value, ioaddr + GMAC_INT_MASK);



#ifdef STMMAC_VLAN_TAG_USED

	/* Tag detection without filtering */
@@ -283,20 +293,20 @@ static int dwmac1000_irq_status(struct mac_device_info *hw, 
	int ret = 0;



	/* Not used events (e.g. MMC interrupts) are not handled. */

	if ((intr_status & mmc_tx_irq))

	if ((intr_status & GMAC_INT_STATUS_MMCTIS))

		x->mmc_tx_irq_n++;

	if (unlikely(intr_status & mmc_rx_irq))

	if (unlikely(intr_status & GMAC_INT_STATUS_MMCRIS))

		x->mmc_rx_irq_n++;

	if (unlikely(intr_status & mmc_rx_csum_offload_irq))

	if (unlikely(intr_status & GMAC_INT_STATUS_MMCCSUM))

		x->mmc_rx_csum_offload_irq_n++;

	if (unlikely(intr_status & pmt_irq)) {

	if (unlikely(intr_status & GMAC_INT_DISABLE_PMT)) {

		/* clear the PMT bits 5 and 6 by reading the PMT status reg */

		readl(ioaddr + GMAC_PMT);

		x->irq_receive_pmt_irq_n++;

	}



	/* MAC trx/rx EEE LPI entry/exit interrupts */

	if (intr_status & lpiis_irq) {

	/* MAC tx/rx EEE LPI entry/exit interrupts */

	if (intr_status & GMAC_INT_STATUS_LPIIS) {

		/* Clean LPI interrupt by reading the Reg 12 */

		ret = readl(ioaddr + LPI_CTRL_STATUS);

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

+9 −0
Original line number Diff line number Diff line
@@ -52,9 +52,18 @@ 
#define GMAC_TX_FLOW_CTRL_PT_SHIFT	16



/*  MAC Interrupt bitmap*/

#define GMAC_INT_RGSMIIS		BIT(0)

#define GMAC_INT_PCS_LINK		BIT(1)

#define GMAC_INT_PCS_ANE		BIT(2)

#define GMAC_INT_PCS_PHYIS		BIT(3)

#define GMAC_INT_PMT_EN			BIT(4)

#define GMAC_INT_LPI_EN			BIT(5)



#define	GMAC_PCS_IRQ_DEFAULT	(GMAC_INT_RGSMIIS | GMAC_INT_PCS_LINK |	\

				 GMAC_INT_PCS_ANE)



#define	GMAC_INT_DEFAULT_MASK	GMAC_INT_PMT_EN



enum dwmac4_irq_status {

	time_stamp_irq = 0x00001000,

	mmc_rx_csum_offload_irq = 0x00000800,

drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c

+7 −1
Original line number Diff line number Diff line
@@ -35,7 +35,13 @@ static void dwmac4_core_init(struct mac_device_info *hw, int mtu) 
	writel(value, ioaddr + GMAC_CONFIG);



	/* Mask GMAC interrupts */

	writel(GMAC_INT_PMT_EN, ioaddr + GMAC_INT_EN);

	value = GMAC_INT_DEFAULT_MASK;

	if (hw->pmt)

		value |= GMAC_INT_PMT_EN;

	if (hw->pcs)

		value |= GMAC_PCS_IRQ_DEFAULT;



	writel(value, ioaddr + GMAC_INT_EN);

}



static void dwmac4_dump_regs(struct mac_device_info *hw)