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Commit 3f1f4311 authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt
Browse files

Merge branch 'merge' into next 

Merge stuff that already went into Linus via "merge" which
are pre-reqs for subsequent patches
parents 5935ff43 28e61cc4

arch/powerpc/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -586,7 +586,7 @@ config SCHED_SMT 
config PPC_DENORMALISATION

	bool "PowerPC denormalisation exception handling"

	depends on PPC_BOOK3S_64

	default "n"

	default "y" if PPC_POWERNV

	---help---

	  Add support for handling denormalisation of single precision

	  values.  Useful for bare metal only.  If unsure say Y here.

arch/powerpc/include/asm/processor.h

+4 −0
Original line number Diff line number Diff line
@@ -247,6 +247,10 @@ struct thread_struct { 
	unsigned long	tm_orig_msr;	/* Thread's MSR on ctx switch */

	struct pt_regs	ckpt_regs;	/* Checkpointed registers */



	unsigned long	tm_tar;

	unsigned long	tm_ppr;

	unsigned long	tm_dscr;



	/*

	 * Transactional FP and VSX 0-31 register set.

	 * NOTE: the sense of these is the opposite of the integer ckpt_regs!

arch/powerpc/include/asm/reg.h

+20 −11
Original line number Diff line number Diff line
@@ -254,19 +254,28 @@ 
#define SPRN_HRMOR	0x139	/* Real mode offset register */

#define SPRN_HSRR0	0x13A	/* Hypervisor Save/Restore 0 */

#define SPRN_HSRR1	0x13B	/* Hypervisor Save/Restore 1 */

/* HFSCR and FSCR bit numbers are the same */

#define FSCR_TAR_LG	8	/* Enable Target Address Register */

#define FSCR_EBB_LG	7	/* Enable Event Based Branching */

#define FSCR_TM_LG	5	/* Enable Transactional Memory */

#define FSCR_PM_LG	4	/* Enable prob/priv access to PMU SPRs */

#define FSCR_BHRB_LG	3	/* Enable Branch History Rolling Buffer*/

#define FSCR_DSCR_LG	2	/* Enable Data Stream Control Register */

#define FSCR_VECVSX_LG	1	/* Enable VMX/VSX  */

#define FSCR_FP_LG	0	/* Enable Floating Point */

#define SPRN_FSCR	0x099	/* Facility Status & Control Register */

#define   FSCR_TAR	(1 << (63-55)) /* Enable Target Address Register */

#define   FSCR_EBB	(1 << (63-56)) /* Enable Event Based Branching */

#define   FSCR_DSCR	(1 << (63-61)) /* Enable Data Stream Control Register */

#define   FSCR_TAR	__MASK(FSCR_TAR_LG)

#define   FSCR_EBB	__MASK(FSCR_EBB_LG)

#define   FSCR_DSCR	__MASK(FSCR_DSCR_LG)

#define SPRN_HFSCR	0xbe	/* HV=1 Facility Status & Control Register */

#define   HFSCR_TAR	(1 << (63-55)) /* Enable Target Address Register */

#define   HFSCR_EBB	(1 << (63-56)) /* Enable Event Based Branching */

#define   HFSCR_TM	(1 << (63-58)) /* Enable Transactional Memory */

#define   HFSCR_PM	(1 << (63-60)) /* Enable prob/priv access to PMU SPRs */

#define   HFSCR_BHRB	(1 << (63-59)) /* Enable Branch History Rolling Buffer*/

#define   HFSCR_DSCR	(1 << (63-61)) /* Enable Data Stream Control Register */

#define   HFSCR_VECVSX	(1 << (63-62)) /* Enable VMX/VSX  */

#define   HFSCR_FP	(1 << (63-63)) /* Enable Floating Point */

#define   HFSCR_TAR	__MASK(FSCR_TAR_LG)

#define   HFSCR_EBB	__MASK(FSCR_EBB_LG)

#define   HFSCR_TM	__MASK(FSCR_TM_LG)

#define   HFSCR_PM	__MASK(FSCR_PM_LG)

#define   HFSCR_BHRB	__MASK(FSCR_BHRB_LG)

#define   HFSCR_DSCR	__MASK(FSCR_DSCR_LG)

#define   HFSCR_VECVSX	__MASK(FSCR_VECVSX_LG)

#define   HFSCR_FP	__MASK(FSCR_FP_LG)

#define SPRN_TAR	0x32f	/* Target Address Register */

#define SPRN_LPCR	0x13E	/* LPAR Control Register */

#define   LPCR_VPM0	(1ul << (63-0))

arch/powerpc/include/asm/switch_to.h

+9 −0
Original line number Diff line number Diff line
@@ -15,6 +15,15 @@ extern struct task_struct *__switch_to(struct task_struct *, 
struct thread_struct;

extern struct task_struct *_switch(struct thread_struct *prev,

				   struct thread_struct *next);

#ifdef CONFIG_PPC_BOOK3S_64

static inline void save_tar(struct thread_struct *prev)

{

	if (cpu_has_feature(CPU_FTR_ARCH_207S))

		prev->tar = mfspr(SPRN_TAR);

}

#else

static inline void save_tar(struct thread_struct *prev) {}

#endif



extern void load_up_fpu(void);

extern void enable_kernel_fp(void);

arch/powerpc/kernel/asm-offsets.c

+3 −0
Original line number Diff line number Diff line
@@ -138,6 +138,9 @@ int main(void) 
	DEFINE(THREAD_TM_TFHAR, offsetof(struct thread_struct, tm_tfhar));

	DEFINE(THREAD_TM_TEXASR, offsetof(struct thread_struct, tm_texasr));

	DEFINE(THREAD_TM_TFIAR, offsetof(struct thread_struct, tm_tfiar));

	DEFINE(THREAD_TM_TAR, offsetof(struct thread_struct, tm_tar));

	DEFINE(THREAD_TM_PPR, offsetof(struct thread_struct, tm_ppr));

	DEFINE(THREAD_TM_DSCR, offsetof(struct thread_struct, tm_dscr));

	DEFINE(PT_CKPT_REGS, offsetof(struct thread_struct, ckpt_regs));

	DEFINE(THREAD_TRANSACT_VR0, offsetof(struct thread_struct,

					 transact_vr[0]));