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Commit 3df22ce3 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "serial: msm_geni_serial: Decide UART sampling rate based on config"

parents 35296724 b6c544aa

drivers/tty/serial/Kconfig

+9 −0
Original line number Diff line number Diff line
@@ -1135,6 +1135,15 @@ config SERIAL_MSM_HS 
	  Choose M here to compile it as a module. The module will be

	  called msm_serial_hs.



config SERIAL_MSM_WITH_HALF_SAMPLING

	bool "Changes clock divider which impacts sampling rate for QUP HW ver greater than 2.5.0"

	depends on SERIAL_MSM_GENI

	help

	  Clock divider value should get double for QUP Hardware version

	  greater than 2.5.0.

	  As earlycon can't have HW version awareness,decision is taken

	  based on the configuration.



config SERIAL_VT8500

	bool "VIA VT8500 on-chip serial port support"

	depends on ARCH_VT8500

drivers/tty/serial/msm_geni_serial.c

+4 −8
Original line number Diff line number Diff line
@@ -131,7 +131,6 @@ 


#define DMA_RX_BUF_SIZE		(2048)

#define UART_CONSOLE_RX_WM	(2)

#define QUP_VER			(0x20050000)



struct msm_geni_serial_ver_info {

	int hw_major_ver;
@@ -210,11 +209,6 @@ static int msm_geni_serial_get_ver_info(struct uart_port *uport); 
static struct msm_geni_serial_port msm_geni_console_port;

static struct msm_geni_serial_port msm_geni_serial_ports[GENI_UART_NR_PORTS];



static int hw_version_info(void __iomem *base_addr)

{

	return geni_read_reg(base_addr, QUPV3_HW_VER);

}



static void msm_geni_serial_config_port(struct uart_port *uport, int cfg_flags)

{

	if (cfg_flags & UART_CONFIG_TYPE)
@@ -1896,8 +1890,9 @@ static void msm_geni_serial_set_termios(struct uart_port *uport, 
	if (clk_div <= 0)

		goto exit_set_termios;



	if (hw_version_info(uport->membase) >= QUP_VER)

	if (IS_ENABLED(CONFIG_SERIAL_MSM_WITH_HALF_SAMPLING))

		clk_div *= 2;



	uport->uartclk = clk_rate;

	clk_set_rate(port->serial_rsc.se_clk, clk_rate);

	ser_clk_cfg |= SER_CLK_EN;
@@ -2193,8 +2188,9 @@ msm_geni_serial_earlycon_setup(struct earlycon_device *dev, 
		goto exit_geni_serial_earlyconsetup;

	}



	if (hw_version_info(uport->membase) >= QUP_VER)

	if (IS_ENABLED(CONFIG_SERIAL_MSM_WITH_HALF_SAMPLING))

		clk_div *= 2;



	s_clk_cfg |= SER_CLK_EN;

	s_clk_cfg |= (clk_div << CLK_DIV_SHFT);