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Commit 3d461401 authored Nov 09, 2010 by Greg Ungerer

m68knommu: move inclusion of ColdFire v4 cache registers

Move the inclusion of the version 4 cache controller registers so that
it is with all the other register bit flag definitions. This makes it
consistent with the other version core inclusion points, and means we
don't need "#ifdef"ery in odd-ball places for these definitions.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>

parent 278c2cbd

arch/m68k/include/asm/cacheflush_no.h

+1 −3

Original line number	Original line	Diff line number	Diff line
	@@ -5,9 +5,7 @@
	* (C) Copyright 2000-2004, Greg Ungerer <gerg@snapgear.com>		* (C) Copyright 2000-2004, Greg Ungerer <gerg@snapgear.com>
	*/		*/
	#include <linux/mm.h>		#include <linux/mm.h>
	#if defined(CONFIG_M5407) \|\| defined(CONFIG_M54xx)		#include <asm/mcfsim.h>
	#include <asm/m54xxacr.h>
	#endif

	#define flush_cache_all() __flush_cache_all()		#define flush_cache_all() __flush_cache_all()
	#define flush_cache_mm(mm) do { } while (0)		#define flush_cache_mm(mm) do { } while (0)

arch/m68k/include/asm/m5407sim.h

+2 −0

Original line number	Original line	Diff line number	Diff line
	@@ -17,6 +17,8 @@
	#define CPU_NAME "COLDFIRE(m5407)"		#define CPU_NAME "COLDFIRE(m5407)"
	#define CPU_INSTR_PER_JIFFY 3		#define CPU_INSTR_PER_JIFFY 3

			#include <asm/m54xxacr.h>

	/*		/*
	* Define the 5407 SIM register set addresses.		* Define the 5407 SIM register set addresses.
	*/		*/

arch/m68k/include/asm/m54xxsim.h

+2 −0

Original line number	Original line	Diff line number	Diff line
	@@ -8,6 +8,8 @@
	#define CPU_NAME "COLDFIRE(m54xx)"		#define CPU_NAME "COLDFIRE(m54xx)"
	#define CPU_INSTR_PER_JIFFY 2		#define CPU_INSTR_PER_JIFFY 2

			#include <asm/m54xxacr.h>

	#define MCFINT_VECBASE 64		#define MCFINT_VECBASE 64

	/*		/*

arch/m68k/include/asm/mcfcache.h

+0 −2

Original line number	Original line	Diff line number	Diff line
	@@ -109,8 +109,6 @@

	#if defined(CONFIG_M5407) \|\| defined(CONFIG_M54xx)		#if defined(CONFIG_M5407) \|\| defined(CONFIG_M54xx)

	#include <asm/m54xxacr.h>

	.macro CACHE_ENABLE		.macro CACHE_ENABLE
	/* invalidate whole cache */		/* invalidate whole cache */
	movel #(CACR_DCINVA+CACR_BCINVA+CACR_ICINVA),%d0		movel #(CACR_DCINVA+CACR_BCINVA+CACR_ICINVA),%d0