Loading drivers/clk/qcom/gcc-qcs405.c +2 −2 Original line number Diff line number Diff line Loading @@ -2838,9 +2838,9 @@ static struct clk_regmap *gcc_qcs405_clocks[] = { static const struct qcom_reset_map gcc_qcs405_resets[] = { [GCC_GENI_IR_BCR] = {0x0F000}, [GCC_USB_HS_BCR] = {0x41000}, [GCC_USB2_HS_PHY_ONLY_BCR] = {0x0000C, 0}, [GCC_USB2_HS_PHY_ONLY_BCR] = {0x41034}, [GCC_QUSB2_PHY_BCR] = {0x4103C}, [GCC_USB_HS_PHY_CFG_AHB_BCR] = {0x41038}, [GCC_USB_HS_PHY_CFG_AHB_BCR] = {0x0000C, 0}, [GCC_USB2A_PHY_BCR] = {0x0000C, 1}, [GCC_USB3_PHY_BCR] = {0x39004}, [GCC_USB_30_BCR] = {0x39000}, Loading Loading
drivers/clk/qcom/gcc-qcs405.c +2 −2 Original line number Diff line number Diff line Loading @@ -2838,9 +2838,9 @@ static struct clk_regmap *gcc_qcs405_clocks[] = { static const struct qcom_reset_map gcc_qcs405_resets[] = { [GCC_GENI_IR_BCR] = {0x0F000}, [GCC_USB_HS_BCR] = {0x41000}, [GCC_USB2_HS_PHY_ONLY_BCR] = {0x0000C, 0}, [GCC_USB2_HS_PHY_ONLY_BCR] = {0x41034}, [GCC_QUSB2_PHY_BCR] = {0x4103C}, [GCC_USB_HS_PHY_CFG_AHB_BCR] = {0x41038}, [GCC_USB_HS_PHY_CFG_AHB_BCR] = {0x0000C, 0}, [GCC_USB2A_PHY_BCR] = {0x0000C, 1}, [GCC_USB3_PHY_BCR] = {0x39004}, [GCC_USB_30_BCR] = {0x39000}, Loading