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Commit 3c5c059c authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add smmu device for sdmmagpie"

parents c37b9826 35cb1eb4

arch/arm64/boot/dts/qcom/msm-arm-smmu-sdmmagpie.dtsi

0 → 100644
+245 −0
Original line number Diff line number Diff line 
/* Copyright (c) 2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#include <dt-bindings/interrupt-controller/arm-gic.h>



&soc {

	kgsl_smmu: arm,smmu-kgsl@5040000 {

		status = "ok";

		compatible = "qcom,smmu-v2";

		reg = <0x5040000 0x10000>;

		#iommu-cells = <1>;

		qcom,dynamic;

		qcom,use-3-lvl-tables;

		qcom,disable-atos;

		#global-interrupts = <2>;

		qcom,regulator-names = "vdd";

		vdd-supply = <&gpu_cx_gdsc>;

		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;

		clock-names = "gcc_gpu_memnoc_gfx_clk";

		clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>;

		attach-impl-defs =

				<0x6000 0x2378>,

				<0x6060 0x1055>,

				<0x678c 0x8>,

				<0x6794 0x28>,

				<0x6800 0x6>,

				<0x6900 0x3ff>,

				<0x6924 0x204>,

				<0x6928 0x11000>,

				<0x6930 0x800>,

				<0x6960 0xffffffff>,

				<0x6b64 0x1a5551>,

				<0x6b68 0x9a82a382>;

	};



	apps_smmu: apps-smmu@0x15000000 {

		compatible = "qcom,qsmmu-v500";

		reg = <0x15000000 0x100000>,

			<0x15182000 0x20>;

		reg-names = "base", "tcu-base";

		#iommu-cells = <2>;

		qcom,skip-init;

		qcom,use-3-lvl-tables;

		#global-interrupts = <1>;

		#size-cells = <1>;

		#address-cells = <1>;

		ranges;

		interrupts =	<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;



		anoc_1_tbu: anoc_1_tbu@0x15185000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x15185000 0x1000>,

				<0x15182200 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x0 0x400>;

			qcom,regulator-names = "vdd";

			vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu1_gdsc>;

		};



		anoc_2_tbu: anoc_2_tbu@0x15189000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x15189000 0x1000>,

				<0x15182208 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x400 0x400>;

			qcom,regulator-names = "vdd";

			vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu2_gdsc>;

		};



		mnoc_hf_0_tbu: mnoc_hf_0_tbu@0x1518d000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x1518d000 0x1000>,

				<0x15182210 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x800 0x400>;

			qcom,regulator-names = "vdd";

			vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>;

		};



		mnoc_hf_1_tbu: mnoc_hf_1_tbu@0x15191000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x15191000 0x1000>,

				<0x15182218 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0xc00 0x400>;

			qcom,regulator-names = "vdd";

			vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc>;

		};



		mnoc_sf_0_tbu: mnoc_sf_0_tbu@0x15195000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x15195000 0x1000>,

				<0x15182220 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x1000 0x400>;

			qcom,regulator-names = "vdd";

			vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc>;

		};



		compute_dsp_0_tbu: compute_dsp_0_tbu@0x15199000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x15199000 0x1000>,

				<0x15182228 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x1400 0x400>;

			/* No GDSC */

		};



		adsp_tbu: adsp_tbu@0x1519d000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x1519d000 0x1000>,

				<0x15182230 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x1800 0x400>;

			qcom,regulator-names = "vdd";

			vdd-supply = <&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc>;

		};



		anoc_1_pcie_tbu: anoc_1_pcie_tbu@0x151a1000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x151a1000 0x1000>,

				<0x15182238 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x1c00 0x400>;

			qcom,regulator-names = "vdd";

			vdd-supply = <&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc>;

			clock-names = "gcc_aggre_noc_pcie_tbu_clk";

			clocks = <&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;

		};

	};



	kgsl_iommu_test_device {

		compatible = "iommu-debug-test";

		iommus = <&kgsl_smmu 0x7>;

	};



	apps_iommu_test_device {

		compatible = "iommu-debug-test";

		iommus = <&apps_smmu 0x21 0>;

	};



	apps_iommu_coherent_test_device {

		compatible = "iommu-debug-test";

		iommus = <&apps_smmu 0x23 0>;

		dma-coherent;

	};

};

arch/arm64/boot/dts/qcom/sdmmagpie-ion.dtsi

0 → 100644
+59 −0
Original line number Diff line number Diff line 
/* Copyright (c) 2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



&soc {

	qcom,ion {

		compatible = "qcom,msm-ion";

		#address-cells = <1>;

		#size-cells = <0>;



		system_heap: qcom,ion-heap@25 {

			reg = <25>;

			qcom,ion-heap-type = "SYSTEM";

		};



		qcom,ion-heap@22 { /* ADSP HEAP */

			reg = <22>;

			memory-region = <&adsp_mem>;

			qcom,ion-heap-type = "DMA";

		};



		qcom,ion-heap@27 { /* QSEECOM HEAP */

			reg = <27>;

			memory-region = <&qseecom_mem>;

			qcom,ion-heap-type = "DMA";

		};



		qcom,ion-heap@19 { /* QSEECOM TA HEAP */

			reg = <19>;

			memory-region = <&qseecom_ta_mem>;

			qcom,ion-heap-type = "DMA";

		};



		qcom,ion-heap@13 { /* SPSS HEAP */

			reg = <13>;

			memory-region = <&sp_mem>;

			qcom,ion-heap-type = "DMA";

		};



		qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */

			reg = <10>;

			memory-region = <&secure_display_memory>;

			qcom,ion-heap-type = "HYP_CMA";

		};



		qcom,ion-heap@9 {

			reg = <9>;

			qcom,ion-heap-type = "SYSTEM_SECURE";

		};

	};

};

arch/arm64/boot/dts/qcom/sdmmagpie.dtsi

+158 −0
Original line number Diff line number Diff line
@@ -336,6 +336,161 @@ 
			};

		};

	};



	reserved-memory {

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;



		hyp_region: hyp_region@85700000 {

			compatible = "removed-dma-pool";

			no-map;

			reg = <0 0x85700000 0 0x600000>;

		};



		xbl_aop_mem: xbl_aop_mem@85e00000 {

			compatible = "removed-dma-pool";

			no-map;

			reg = <0x0 0x85e00000 0x0 0x1ff000>;

		};



		sec_apps_mem: sec_apps_region@85fff000 {

			compatible = "removed-dma-pool";

			no-map;

			reg = <0x0 0x85fff000 0x0 0x1000>;

		};



		smem_region: smem@86000000 {

			compatible = "removed-dma-pool";

			no-map;

			reg = <0x0 0x86000000 0x0 0x200000>;

		};



		removed_region: removed_region@86200000 {

			compatible = "removed-dma-pool";

			no-map;

			reg = <0 0x86200000 0 0x2d00000>;

		};



		pil_camera_mem: camera_region@8ab00000 {

			compatible = "removed-dma-pool";

			no-map;

			reg = <0 0x8ab00000 0 0x500000>;

		};



		pil_modem_mem: modem_region@8b000000 {

			compatible = "removed-dma-pool";

			no-map;

			reg = <0 0x8b000000 0 0x7e00000>;

		};



		pil_video_mem: pil_video_region@92e00000 {

			compatible = "removed-dma-pool";

			no-map;

			reg = <0 0x92e00000 0 0x500000>;

		};



		wlan_msa_mem: wlan_msa_region@93300000 {

			compatible = "removed-dma-pool";

			no-map;

			reg = <0 0x93300000 0 0x100000>;

		};



		pil_cdsp_mem: cdsp_regions@93400000 {

			compatible = "removed-dma-pool";

			no-map;

			reg = <0 0x93400000 0 0x800000>;

		};



		pil_adsp_mem: pil_adsp_region@93c00000 {

			compatible = "removed-dma-pool";

			no-map;

			reg = <0 0x93c00000 0 0x1e00000>;

		};



		pil_ipa_fw_mem: ips_fw_region@95a00000 {

			compatible = "removed-dma-pool";

			no-map;

			reg = <0 0x95a00000 0 0x10000>;

		};



		pil_ipa_gsi_mem: ipa_gsi_region@95a10000 {

			compatible = "removed-dma-pool";

			no-map;

			reg = <0 0x95a10000 0 0x5000>;

		};



		pil_gpu_mem: gpu_region@95a15000 {

			compatible = "removed-dma-pool";

			no-map;

			reg = <0 0x95a15000 0 0x2000>;

		};



		npu_mem: npu_region@95a80000 {

			compatible = "removed-dma-pool";

			no-map;

			reg = <0 0x95a80000 0 0x80000>;

		};



		qseecom_mem: qseecom_region@9e400000 {

			compatible = "shared-dma-pool";

			no-map;

			reg = <0 0x9e400000 0 0x1400000>;

		};



		adsp_mem: adsp_region {

			compatible = "shared-dma-pool";

			alloc-ranges = <0 0x00000000 0 0xffffffff>;

			reusable;

			alignment = <0 0x400000>;

			size = <0 0xc00000>;

		};



		qseecom_ta_mem: qseecom_ta_region {

			compatible = "shared-dma-pool";

			alloc-ranges = <0 0x00000000 0 0xffffffff>;

			reusable;

			alignment = <0 0x400000>;

			size = <0 0x1000000>;

		};



		sp_mem: sp_region {  /* SPSS-HLOS ION shared mem */

			compatible = "shared-dma-pool";

			alloc-ranges = <0 0x00000000 0 0xffffffff>; /* 32-bit */

			reusable;

			alignment = <0 0x400000>;

			size = <0 0x800000>;

		};



		secure_display_memory: secure_display_region {

			compatible = "shared-dma-pool";

			alloc-ranges = <0 0x00000000 0 0xffffffff>;

			reusable;

			alignment = <0 0x400000>;

			size = <0 0x5c00000>;

		};



		cont_splash_memory: cont_splash_region@9d400000 {

			reg = <0x0 0x9d400000 0x0 0x02400000>;

			label = "cont_splash_region";

		};



		dump_mem: mem_dump_region {

			compatible = "shared-dma-pool";

			reusable;

			size = <0 0x2400000>;

		};



		/* global autoconfigured region for contiguous allocations */

		linux,cma {

			compatible = "shared-dma-pool";

			alloc-ranges = <0 0x00000000 0 0xffffffff>;

			reusable;

			alignment = <0 0x400000>;

			size = <0 0x2000000>;

			linux,cma-default;

		};

	};

};



&soc {
@@ -816,3 +971,6 @@ 
&npu_core_gdsc {

	status = "ok";

};



#include "sdmmagpie-ion.dtsi"

#include "msm-arm-smmu-sdmmagpie.dtsi"