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Commit 3c0ff9f1 authored by Leo Liu's avatar Leo Liu Committed by Alex Deucher
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drm/amdgpu: vce use multiple cache surface starting from stoney 



Signed-off-by: default avatarLeo Liu <leo.liu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d6c29c30

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

+14 −5
Original line number Original line Diff line number Diff line
@@ -40,6 +40,9 @@ 




#define GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT	0x04

#define GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT	0x04

#define GRBM_GFX_INDEX__VCE_INSTANCE_MASK	0x10

#define GRBM_GFX_INDEX__VCE_INSTANCE_MASK	0x10

#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0 	0x8616

#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1 	0x8617

#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2 	0x8618





#define VCE_V3_0_FW_SIZE	(384 * 1024)

#define VCE_V3_0_FW_SIZE	(384 * 1024)

#define VCE_V3_0_STACK_SIZE	(64 * 1024)

#define VCE_V3_0_STACK_SIZE	(64 * 1024)
@@ -130,7 +133,9 @@ static int vce_v3_0_start(struct amdgpu_device *adev) 




		/* set BUSY flag */

		/* set BUSY flag */

		WREG32_P(mmVCE_STATUS, 1, ~1);

		WREG32_P(mmVCE_STATUS, 1, ~1);



		if (adev->asic_type >= CHIP_STONEY)

			WREG32_P(mmVCE_VCPU_CNTL, 1, ~0x200001);

		else

			WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK,

			WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK,

				~VCE_VCPU_CNTL__CLK_EN_MASK);

				~VCE_VCPU_CNTL__CLK_EN_MASK);
@@ -391,7 +396,11 @@ static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx) 
	WREG32(mmVCE_LMI_SWAP_CNTL, 0);

	WREG32(mmVCE_LMI_SWAP_CNTL, 0);

	WREG32(mmVCE_LMI_SWAP_CNTL1, 0);

	WREG32(mmVCE_LMI_SWAP_CNTL1, 0);

	WREG32(mmVCE_LMI_VM_CTRL, 0);

	WREG32(mmVCE_LMI_VM_CTRL, 0);



	if (adev->asic_type >= CHIP_STONEY) {

		WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8));

		WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR1, (adev->vce.gpu_addr >> 8));

		WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR2, (adev->vce.gpu_addr >> 8));

	} else

		WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8));

		WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8));

	offset = AMDGPU_VCE_FIRMWARE_OFFSET;

	offset = AMDGPU_VCE_FIRMWARE_OFFSET;

	size = VCE_V3_0_FW_SIZE;

	size = VCE_V3_0_FW_SIZE;