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Commit 3b4c552e authored by Sankeerth Billakanti's avatar Sankeerth Billakanti
Browse files

drm/msm/dp: use extended DPCD fields to configure dp link rate 



Use the EXTENDED_RECEIVER_CAPABILITY DPCD register fields,
if present, for enabling HBR3 link rate on supported targets.

Change-Id: I505d998f31f79162dc290fc47fd9fbba51527982
Signed-off-by: default avatarSankeerth Billakanti <sbillaka@codeaurora.org>
parent 16b2abac

drivers/gpu/drm/msm/dp/dp_panel.c

+7 −1
Original line number Diff line number Diff line
@@ -1646,13 +1646,16 @@ static int dp_panel_read_dpcd(struct dp_panel *dp_panel, bool multi_func) 
		panel->vscext_chaining_supported);



skip_dpcd_read:

	link_info->revision = dpcd[DP_DPCD_REV];

	panel->major = (link_info->revision >> 4) & 0x0f;

	panel->minor = link_info->revision & 0x0f;



	/* override link params updated in dp_panel_init_panel_info */

	link_info->rate = min_t(unsigned long, panel->parser->max_lclk_khz,

				link_info->rate);

			drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]));



	link_info->num_lanes = dpcd[DP_MAX_LANE_COUNT] &

				DP_MAX_LANE_COUNT_MASK;

	if (multi_func)

		link_info->num_lanes = min_t(unsigned int,

			link_info->num_lanes, 2);
@@ -1660,6 +1663,9 @@ static int dp_panel_read_dpcd(struct dp_panel *dp_panel, bool multi_func) 
	pr_debug("version:%d.%d, rate:%d, lanes:%d\n", panel->major,

		panel->minor, link_info->rate, link_info->num_lanes);



	if (drm_dp_enhanced_frame_cap(dpcd))

		link_info->capabilities |= DP_LINK_CAP_ENHANCED_FRAMING;



	dfp_count = dpcd[DP_DOWN_STREAM_PORT_COUNT] &

						DP_DOWN_STREAM_PORT_COUNT;