Merge "clk: qcom: mdss: update the names for DP 10nm PLL clocks" (3ad92b26) · Commits · e / devices / android_kernel_oneplus_sm8150

arch/arm64/boot/dts/qcom/sdmmagpie.dtsi

+11 −0

Original line number	Diff line number	Diff line
		@@ -3005,6 +3005,17 @@
		#include "sdmmagpie-coresight.dtsi"
		#include "sdmmagpie-usb.dtsi"
		#include "sdmmagpie-thermal.dtsi"

		&qupv3_se9_i2c {
		status = "ok";
		fsa4480: fsa4480@43 {
		compatible = "qcom,fsa4480-i2c";
		reg = <0x43>;
		pinctrl-names = "default";
		pinctrl-0 = <&fsa_usbc_ana_en>;
		};
		};

		#include "sdmmagpie-audio.dtsi"

		&usb0 {

arch/arm64/boot/dts/qcom/sm6150-audio.dtsi

+0 −10

Original line number	Diff line number	Diff line
		@@ -146,13 +146,3 @@
		elemental-addr = [ff ff ff fe 17 02];
		};
		};

		&qupv3_se3_i2c {
		status = "ok";
		fsa4480: fsa4480@43 {
		compatible = "qcom,fsa4480-i2c";
		reg = <0x43>;
		pinctrl-names = "default";
		pinctrl-0 = <&fsa_usbc_ana_en>;
		};
		};

arch/arm64/boot/dts/qcom/sm6150.dtsi

+10 −0

Original line number	Diff line number	Diff line
		@@ -3142,6 +3142,16 @@
		status = "ok";
		};

		&qupv3_se3_i2c {
		status = "ok";
		fsa4480: fsa4480@43 {
		compatible = "qcom,fsa4480-i2c";
		reg = <0x43>;
		pinctrl-names = "default";
		pinctrl-0 = <&fsa_usbc_ana_en>;
		};
		};

		#include "sm6150-camera.dtsi"
		#include "sm6150-ion.dtsi"
		#include "msm-arm-smmu-sm6150.dtsi"

drivers/clk/qcom/mdss/mdss-dp-pll-10nm.c

+8 −8

Original line number	Diff line number	Diff line
		/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
		/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		@@ -108,12 +108,12 @@ static struct dp_pll_vco_clk dp_vco_clk = {
		},
		};

		static struct clk_fixed_factor dp_link_clk_divsel_ten = {
		static struct clk_fixed_factor dp_phy_pll_link_clk = {
		.div = 10,
		.mult = 1,

		.hw.init = &(struct clk_init_data){
		.name = "dp_link_clk_divsel_ten",
		.name = "dp_phy_pll_link_clk",
		.parent_names =
		(const char *[]){ "dp_vco_clk" },
		.num_parents = 1,
		@@ -207,14 +207,14 @@ static unsigned long mux_recalc_rate(struct clk_hw *hw,
		return (vco->rate / 2);
		}

		static struct clk_regmap_mux dp_vco_divided_clk_src_mux = {
		static struct clk_regmap_mux dp_phy_pll_vco_div_clk = {
		.reg = 0x64,
		.shift = 0,
		.width = 2,

		.clkr = {
		.hw.init = &(struct clk_init_data){
		.name = "dp_vco_divided_clk_src_mux",
		.name = "dp_phy_pll_vco_div_clk",
		.parent_names =
		(const char *[]){"dp_vco_divsel_two_clk_src",
		"dp_vco_divsel_four_clk_src",
		@@ -228,11 +228,11 @@ static struct clk_regmap_mux dp_vco_divided_clk_src_mux = {

		static struct clk_hw *mdss_dp_pllcc_10nm[] = {
		[DP_VCO_CLK] = &dp_vco_clk.hw,
		[DP_LINK_CLK_DIVSEL_TEN] = &dp_link_clk_divsel_ten.hw,
		[DP_LINK_CLK_DIVSEL_TEN] = &dp_phy_pll_link_clk.hw,
		[DP_VCO_DIVIDED_TWO_CLK_SRC] = &dp_vco_divsel_two_clk_src.hw,
		[DP_VCO_DIVIDED_FOUR_CLK_SRC] = &dp_vco_divsel_four_clk_src.hw,
		[DP_VCO_DIVIDED_SIX_CLK_SRC] = &dp_vco_divsel_six_clk_src.hw,
		[DP_VCO_DIVIDED_CLK_SRC_MUX] = &dp_vco_divided_clk_src_mux.clkr.hw,
		[DP_VCO_DIVIDED_CLK_SRC_MUX] = &dp_phy_pll_vco_div_clk.clkr.hw,
		};

		int dp_pll_clock_register_10nm(struct platform_device *pdev,
		@@ -274,7 +274,7 @@ int dp_pll_clock_register_10nm(struct platform_device *pdev,
		/* Set client data for vco, mux and div clocks */
		regmap = devm_regmap_init(&pdev->dev, &dp_pixel_mux_regmap_ops,
		pll_res, &dp_pll_10nm_cfg);
		dp_vco_divided_clk_src_mux.clkr.regmap = regmap;
		dp_phy_pll_vco_div_clk.clkr.regmap = regmap;
		mux_clk_ops = clk_regmap_mux_closest_ops;
		mux_clk_ops.determine_rate = clk_mux_determine_rate;
		mux_clk_ops.recalc_rate = mux_recalc_rate;