Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 3a7f1f37 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
Browse files

Merge "power: qpnp-fg-gen4: Add support to configure battery thermistor interval"

parents 1c2b0efa c373b54b

Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen4.txt

+7 −0
Original line number Diff line number Diff line
@@ -190,6 +190,13 @@ First Level Node - FG Gen4 device 
	Definition: Battery temperature hysteresis threshold. Possible values

		    are: 0, 1, 2 and 3. Unit is in Kelvin or Celsius.



- qcom,fg-batt-therm-freq

	Usage:      optional

	Value type: <u32>

	Definition: Battery thermistor interval in seconds. Possible values

		    are from 1-255. If not specified, then the default value

		    configured is 8.



- qcom,fg-force-load-profile

	Usage:      optional

	Value type: <empty>

drivers/power/supply/qcom/fg-reg.h

+2 −0
Original line number Diff line number Diff line
@@ -41,6 +41,8 @@ 
#define BATT_THERM_PULL_UP_400K			3

#define BATT_THERM_PULL_UP_MASK			GENMASK(1, 0)



#define ADC_RR_BATT_THERM_FREQ(chip)		(chip->rradc_base + 0x82)



#define ADC_RR_BATT_TEMP_LSB(chip)		(chip->rradc_base + 0x88)

#define ADC_RR_BATT_TEMP_MSB(chip)		(chip->rradc_base + 0x89)

#define GEN4_BATT_TEMP_MSB_MASK			GENMASK(1, 0)

drivers/power/supply/qcom/qpnp-fg-gen4.c

+14 −0
Original line number Diff line number Diff line
@@ -208,6 +208,7 @@ struct fg_dt_props { 
	int	batt_temp_hot_thresh;

	int	batt_temp_hyst;

	int	batt_temp_delta;

	u32	batt_therm_freq;

	int	esr_pulse_thresh_ma;

	int	esr_meas_curr_ma;

	int	slope_limit_temp;
@@ -4020,6 +4021,14 @@ static int fg_gen4_hw_init(struct fg_gen4_chip *chip) 
		}

	}



	val = (u8)chip->dt.batt_therm_freq;

	rc = fg_write(fg, ADC_RR_BATT_THERM_FREQ(fg), &val, 1);

	if (rc < 0) {

		pr_err("failed to write to 0x%04X, rc=%d\n",

			 ADC_RR_BATT_THERM_FREQ(fg), rc);

		return rc;

	}



	fg_encode(fg->sp, FG_SRAM_ESR_PULSE_THRESH,

		chip->dt.esr_pulse_thresh_ma, buf);

	rc = fg_sram_write(fg, fg->sp[FG_SRAM_ESR_PULSE_THRESH].addr_word,
@@ -4612,6 +4621,11 @@ static int fg_gen4_parse_dt(struct fg_gen4_chip *chip) 
	else if (temp >= BTEMP_DELTA_LOW && temp <= BTEMP_DELTA_HIGH)

		chip->dt.batt_temp_delta = temp;



	chip->dt.batt_therm_freq = 8;

	rc = of_property_read_u32(node, "qcom,fg-batt-therm-freq", &temp);

	if (temp > 0 && temp <= 255)

		chip->dt.batt_therm_freq = temp;



	chip->dt.hold_soc_while_full = of_property_read_bool(node,

					"qcom,hold-soc-while-full");