Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 39b3a791 authored by Andi Kleen's avatar Andi Kleen Committed by Linus Torvalds
Browse files

[PATCH] i386/x86-64: Generalize X86_FEATURE_CONSTANT_TSC flag 



Define it for i386 too.

This is a synthetic flag that signifies that the CPU's TSC runs
at a constant P state invariant frequency.

Fix up the logic on x86-64/i386 to set it on all known CPUs.
Use the AMD defined bit to set it on future AMD CPUs.

Cc: venkatesh.pallipadi@intel.com

Signed-off-by: default avatarAndi Kleen <ak@suse.de>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 2d52ede9

arch/i386/kernel/cpu/amd.c

+6 −0
Original line number Diff line number Diff line
@@ -216,6 +216,11 @@ static void __init init_amd(struct cpuinfo_x86 *c) 
			c->x86_max_cores = 1;

	}



	if (cpuid_eax(0x80000000) >= 0x80000007) {

		if (cpuid_edx(0x80000007) & (1<<8))

			set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);

	}



#ifdef CONFIG_X86_HT

	/*

	 * On a AMD dual core setup the lower bits of the APIC id
@@ -233,6 +238,7 @@ static void __init init_amd(struct cpuinfo_x86 *c) 
		       cpu, c->x86_max_cores, cpu_core_id[cpu]);

	}

#endif



}



static unsigned int amd_size_cache(struct cpuinfo_x86 * c, unsigned int size)

arch/i386/kernel/cpu/intel.c

+4 −1
Original line number Diff line number Diff line
@@ -187,6 +187,9 @@ static void __devinit init_intel(struct cpuinfo_x86 *c) 
		set_bit(X86_FEATURE_P4, c->x86_capability);

	if (c->x86 == 6) 

		set_bit(X86_FEATURE_P3, c->x86_capability);

	if ((c->x86 == 0xf && c->x86_model >= 0x03) ||

		(c->x86 == 0x6 && c->x86_model >= 0x0e))

		set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);

}

arch/i386/kernel/cpu/proc.c

+1 −1
Original line number Diff line number Diff line
@@ -40,7 +40,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) 
		/* Other (Linux-defined) */

		"cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr",

		NULL, NULL, NULL, NULL,

		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

		"constant_tsc", NULL, NULL, NULL, NULL, NULL, NULL, NULL,

		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

arch/x86_64/kernel/setup.c

+3 −2
Original line number Diff line number Diff line
@@ -1032,7 +1032,8 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c) 


	if (c->x86 == 15)

		c->x86_cache_alignment = c->x86_clflush_size * 2;

	if (c->x86 >= 15)

	if ((c->x86 == 0xf && c->x86_model >= 0x03) ||

	    (c->x86 == 0x6 && c->x86_model >= 0x0e))

		set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);

 	c->x86_max_cores = intel_num_cpu_cores(c);
@@ -1273,7 +1274,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) 
		"tm",

		"stc"

		"?",

		"constant_tsc",

		/* nothing */	/* constant_tsc - moved to flags */

	};

include/asm-i386/cpufeature.h

+1 −0
Original line number Diff line number Diff line
@@ -69,6 +69,7 @@ 
#define X86_FEATURE_K7		(3*32+ 5) /* Athlon */

#define X86_FEATURE_P3		(3*32+ 6) /* P3 */

#define X86_FEATURE_P4		(3*32+ 7) /* P4 */

#define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */



/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */

#define X86_FEATURE_XMM3	(4*32+ 0) /* Streaming SIMD Extensions-3 */