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Commit 397c1d9f authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "clk: qcom: clk-cpu-qcs405: Add support for vdd_hf_pll regulator"

parents 26fe56f4 1ec7355b

Documentation/devicetree/bindings/clock/qcom,qcs405-cpucc.txt

+4 −2
Original line number Diff line number Diff line
@@ -13,7 +13,8 @@ Required properties: 
- reg:	Shall contain base register offset and size.

- reg-names:	Names of the bases for the above registers. Shall contain following:

		"apcs_cmd", "apcs_pll"

- vdd_dig_ao-supply:	The regulator powering the APSS PLL.

- vdd_dig_ao-supply:	The regulator(active only) powering the digital logic of APSS PLL.

- vdd_hf_pll-supply:	The regulator(active only) powering the Analog logic of APSS PLL.

- cpu-vdd-supply:	The regulator powering the APSS RCG.

- qcom,speedX-bin-vZ:	A table of CPU frequency (Hz) to regulator voltage (uV) mapping.

			Format: <freq uV>
@@ -37,7 +38,8 @@ Example: 
			<0xb016000 0x34>;

		reg-names = "apcs_cmd" , "apcs_pll";

		cpu-vdd-supply = <&apc_vreg_corner>;

		vdd_dig_ao-supply = <&pmd9655_s1_level>;

		vdd_dig_ao-supply = <&pmd9655_s1_level_ao>;

		vdd_hf_pll-supply = <&pms405_l5_ao>;

		qcom,speed0-bin-v0 =

			< 0         0>,

			< 960000000  1>,

arch/arm64/boot/dts/qcom/qcs405.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -327,7 +327,8 @@ 
			<0xb016000 0x34>;

		reg-names = "apcs_cmd" , "apcs_pll";

		cpu-vdd-supply = <&apc_vreg_corner>;

		vdd_dig_ao-supply = <&pms405_s1_level>;

		vdd_dig_ao-supply = <&pms405_s1_level_ao>;

		vdd_hf_pll-supply = <&pms405_l5_ao>;

		qcom,speed0-bin-v0 =

			< 0         0>,

			< 1113600000 1>,

drivers/clk/qcom/clk-cpu-qcs405.c

+18 −10
Original line number Diff line number Diff line
@@ -36,7 +36,7 @@ 
#define APCS_CMD	0x0b011050

#define XO_RATE		19200000



static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner);

static DEFINE_VDD_REGULATORS(vdd_hf_pll, VDD_HF_PLL_NUM, 2, vdd_hf_levels);

static DEFINE_VDD_REGS_INIT(vdd_cpu, 1);

static unsigned int cpucc_clk_init_rate;
@@ -265,12 +265,12 @@ static struct clk_pll apcs_cpu_pll = { 
		.parent_names = (const char *[]){ "cxo_a" },

		.num_parents = 1,

		.ops = &clk_pll_hf_ops,

		.vdd_class = &vdd_cx,

		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_LOW] = 1000000000,

			[VDD_NOMINAL] = 2000000000,

		.vdd_class = &vdd_hf_pll,

		.rate_max = (unsigned long[VDD_HF_PLL_NUM]) {

			[VDD_HF_PLL_SVS] = 1000000000,

			[VDD_HF_PLL_NOM] = 2000000000,

		},

		.num_rate_max = VDD_NUM,

		.num_rate_max = VDD_HF_PLL_NUM,

	},

};
@@ -533,12 +533,20 @@ static int cpucc_driver_probe(struct platform_device *pdev) 
	}



	 /* Rail Regulator for apcs_pll */

	vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig_ao");

	if (IS_ERR(vdd_cx.regulator[0])) {

		if (!(PTR_ERR(vdd_cx.regulator[0]) == -EPROBE_DEFER))

	vdd_hf_pll.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_hf_pll");

	if (IS_ERR(vdd_hf_pll.regulator[0])) {

		if (!(PTR_ERR(vdd_hf_pll.regulator[0]) == -EPROBE_DEFER))

			dev_err(&pdev->dev,

				"Unable to get vdd_hf_pll regulator\n");

		return PTR_ERR(vdd_hf_pll.regulator[0]);

	}



	vdd_hf_pll.regulator[1] = devm_regulator_get(&pdev->dev, "vdd_dig_ao");

	if (IS_ERR(vdd_hf_pll.regulator[1])) {

		if (!(PTR_ERR(vdd_hf_pll.regulator[1]) == -EPROBE_DEFER))

			dev_err(&pdev->dev,

				"Unable to get vdd_dig_ao regulator\n");

		return PTR_ERR(vdd_cx.regulator[0]);

		return PTR_ERR(vdd_hf_pll.regulator[1]);

	}



	/* Rail Regulator for APSS cpuss mux */

drivers/clk/qcom/vdd-level-405.h

+15 −0
Original line number Diff line number Diff line
@@ -40,4 +40,19 @@ static int vdd_corner[] = { 
	RPM_REGULATOR_LEVEL_TURBO,		/* VDD_HIGH */

};



enum vdd_hf_pll_levels {

	VDD_HF_PLL_OFF,

	VDD_HF_PLL_SVS,

	VDD_HF_PLL_NOM,

	VDD_HF_PLL_TUR,

	VDD_HF_PLL_NUM,

};



static int vdd_hf_levels[] = {

	0,       RPM_REGULATOR_LEVEL_NONE,	/* VDD_HF_PLL_OFF */

	1800000, RPM_REGULATOR_LEVEL_SVS,	/* VDD_HF_PLL_SVS */

	1800000, RPM_REGULATOR_LEVEL_NOM,	/* VDD_HF_PLL_NOM */

	1800000, RPM_REGULATOR_LEVEL_TURBO,	/* VDD_HF_PLL_TUR */

};



#endif