Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 395b2913 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Fix a few bad hex numbers in register defines 



A few register mask defines were missing the '0x' from hex numbers. Or
at least I assume those were meant to be hex numbers. Put the '0x' in
place.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 68d97538

drivers/gpu/drm/i915/i915_reg.h

+2 −2
Original line number Diff line number Diff line
@@ -4284,7 +4284,7 @@ enum skl_disp_power_wells { 
#define   DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL	(1 << 14)

#define   DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL	(1 << 13)

#define   DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL	(1 << 12)

#define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (1f << 5)

#define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)

#define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)

#define   DP_AUX_CH_CTL_SYNC_PULSE_SKL(c)   ((c) - 1)
@@ -7979,7 +7979,7 @@ enum skl_disp_power_wells { 
#define  VIRTUAL_CHANNEL_SHIFT				6

#define  VIRTUAL_CHANNEL_MASK				(3 << 6)

#define  DATA_TYPE_SHIFT				0

#define  DATA_TYPE_MASK					(3f << 0)

#define  DATA_TYPE_MASK					(0x3f << 0)

/* data type values, see include/video/mipi_display.h */



#define _MIPIA_GEN_FIFO_STAT		(dev_priv->mipi_mmio_base + 0xb074)