Merge remote-tracking branch 'quic/msm-4.14' into dev/msm-4.14-display (394c559c) · Commits · e / devices / android_kernel_oneplus_sm8150

Documentation/admin-guide/kernel-parameters.txt

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		@@ -4006,6 +4006,23 @@
		expediting. Set to zero to disable automatic
		expediting.

		ssbd= [ARM64,HW]
		Speculative Store Bypass Disable control

		On CPUs that are vulnerable to the Speculative
		Store Bypass vulnerability and offer a
		firmware based mitigation, this parameter
		indicates how the mitigation should be used:

		force-on: Unconditionally enable mitigation for
		for both kernel and userspace
		force-off: Unconditionally disable mitigation for
		for both kernel and userspace
		kernel: Always enable mitigation in the
		kernel, and offer a prctl interface
		to allow userspace to register its
		interest in being mitigated too.

		stack_guard_gap= [MM]
		override the default stack gap protection. The value
		is in page units and it defines how many pages prior

Documentation/devicetree/bindings/arm/msm/rpm-smd.txt

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		@@ -10,18 +10,18 @@ the application processor, the modem processor, as well as hardware
		accelerators. The RPM driver communicates with the hardware engine using
		SMD.

		The devicetree representation of the SPM block should be:
		The devicetree representation of the RPM block should be:

		Required properties

		- compatible: "qcom,rpm-smd" or "qcom,rpm-glink"
		- compatible: "qcom,rpm-smd"
		- rpm-channel-name: The string corresponding to the channel name of the
		peripheral subsystem. Required for both smd and
		glink transports.
		- rpm-channel-type: The interal SMD edge for this subsystem found in
		<soc/qcom/smd.h>
		- qcom,glink-edge: Logical name of the remote subsystem. This is a required
		property when rpm-smd driver using glink as trasport.
		- interrupts: The IRQ used by remote processor to inform APSS about
		reception of response message packet.

		Optional properties
		- rpm-standalone: Allow RPM driver to run in standalone mode irrespective of RPM
		@@ -32,10 +32,10 @@ Optional properties
		Example:

		qcom,rpm-smd@68150 {
		compatible = "qcom,rpm-smd", "qcom,rpm-glink";
		compatible = "qcom,rpm-smd";
		reg = <0x68150 0x3200>;
		interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
		qcom,rpm-channel-name = "rpm_requests";
		qcom,rpm-channel-type = 15; /* SMD_APPS_RPM */
		qcom,glink-edge = "rpm";
		}
		}

Documentation/devicetree/bindings/interrupt-controller/qti,pdc-sdmmagpie.txt

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		QTI PDC interrupt controller

		PDC is QTI's platform parent interrupt controller that serves as wakeup source.

		Newer QTI SOCs are replacing MPM (MSM sleep Power Manager) with PDC (Power
		Domain Controller) to manage subsystem wakeups and resources during sleep.
		This driver marks the wakeup interrupts in APSS PDC such that it monitors the
		interrupts when the system is asleep, wakes up the APSS when one of these
		interrupts occur and replays it to the subsystem interrupt controller after it
		becomes operational.

		Earlier MPM architecture used arch-extension of GIC interrupt
		controller to mark enabled wake-up interrupts and monitor these when the
		system goes to sleep. Since the arch-extensions are no-longer available
		on newer kernel versions, this driver is implemented as hierarchical irq
		domain. GIC is parent interrupt controller at the highest level.
		Platform interrupt controller PDC is next in hierarchy, followed by others.
		This driver only configures the interrupts, does not handle them.

		PDC interrupt configuration involves programming of 2 set of registers:
		IRQ_ENABLE_BANK - Enable the irq
		IRQ_i_CFG - Configure the interrupt i

		Properties:

		- compatible:
		Usage: required
		Value type: <string>
		Definition: Should contain "qcom,pdc-<target>"

		- reg:
		Usage: required
		Value type: <prop-encoded-array>
		Definition: Specifies the base physical address for PDC hardware
		block for DRV2.

		- interrupt-cells:
		Usage: required
		Value type: <u32>
		Definition: Specifies the number of cells needed to encode an interrupt source.
		Value must be 3.
		The encoding of these cells are same as described in
		Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt

		- interrupt-parent:
		Usage: required
		Value type: <phandle>
		Definition: Specifies the interrupt parent necessary for hierarchical domain to operate.

		- interrupt-controller:
		Usage: required
		Value type: <bool>
		Definition: Identifies the node as an interrupt controller.

		Example:

		pdcgic: interrupt-controller@0xb220000{
		compatible = "qcom,pdc-sdmmagpie";
		reg = <0xb220000 0x30000>;
		#interrupt-cells = <3>;
		interrupt-parent = <&intc>;
		interrupt-controller;
		};

Documentation/devicetree/bindings/pinctrl/qcom,lpi-pinctrl.txt

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		Qualcomm Technologies, Inc. LPI GPIO controller driver

		This DT bindings describes the GPIO controller driver
		being added for supporting LPI (Low Power Island) TLMM
		from QTI chipsets.

		Following properties are for LPI GPIO controller device main node.
		- compatible:
		Usage: required
		Value type: <string>
		Definition: must be "qcom,lpi-pinctrl"

		- reg:
		Usage: required
		Value type: <prop-encoded-array>
		Definition: Register base of the GPIO controller and length.

		- qcom,num-gpios:
		Usage: required
		Value type: <u32>
		Definition: Number of GPIOs supported by the controller.

		- qcom,lpi-offset-tbl
		Usage: required
		Value type: <u32-array>
		Definition: Offset table of GPIOs supported by the controller.

		- gpio-controller:
		Usage: required
		Value type: <none>
		Definition: Used to mark the device node as a GPIO controller.

		- #gpio-cells:
		Usage: required
		Value type: <u32>
		Definition: Must be 2;
		The first cell will be used to define gpio number and the
		second denotes the flags for this gpio.

		Please refer to ../gpio/gpio.txt for general description of GPIO bindings.

		Please refer to pinctrl-bindings.txt in this directory for details of the
		common pinctrl bindings used by client devices, including the meaning of the
		phrase "pin configuration node".

		The pin configuration nodes act as a container for an arbitrary number of
		subnodes. Each of these subnodes represents some desired configuration for a
		pin or a list of pins. This configuration can include the
		mux function to select on those pin(s), and various pin configuration
		parameters, as listed below.

		SUBNODES:

		The name of each subnode is not important; all subnodes should be enumerated
		and processed purely based on their content.

		Each subnode only affects those parameters that are explicitly listed. In
		other words, a subnode that lists a mux function but no pin configuration
		parameters implies no information about any pin configuration parameters.
		Similarly, a pin subnode that describes a pullup parameter implies no
		information about e.g. the mux function.

		The following generic properties as defined in pinctrl-bindings.txt are valid
		to specify in a pin configuration subnode:

		- pins:
		Usage: required
		Value type: <string-array>
		Definition: List of gpio pins affected by the properties specified in
		this subnode. Valid pins are: gpio0-gpio31 for LPI.

		- function:
		Usage: required
		Value type: <string>
		Definition: Specify the alternative function to be configured for the
		specified pins. Valid values are:
		"gpio",
		"func1",
		"func2",
		"func3",
		"func4",
		"func5"

		- bias-disable:
		Usage: optional
		Value type: <none>
		Definition: The specified pins should be configured as no pull.

		- bias-pull-down:
		Usage: optional
		Value type: <none>
		Definition: The specified pins should be configured as pull down.

		- bias-bus-hold:
		Usage: optional
		Value type: <none>
		Definition: The specified pins should be configured as bus-keeper mode.

		- bias-pull-up:
		Usage: optional
		Value type: <empty>
		Definition: The specified pins should be configured as pull up.

		- input-enable:
		Usage: optional
		Value type: <none>
		Definition: The specified pins are put in input mode.

		- output-high:
		Usage: optional
		Value type: <none>
		Definition: The specified pins are configured in output mode, driven
		high.

		- output-low:
		Usage: optional
		Value type: <none>
		Definition: The specified pins are configured in output mode, driven
		low.

		- qcom,drive-strength:
		Usage: optional
		Value type: <u32>
		Definition: Selects the drive strength for the specified pins.

		Example:

		lpi_tlmm: lpi_pinctrl@152c000 {
		compatible = "qcom,lpi-pinctrl";
		qcom,num-gpios = <32>;
		reg = <0x152c000 0>;
		gpio-controller;
		#gpio-cells = <2>;
		qcom,lpi-offset-tbl = <0x00000010>, <0x00000020>,
		<0x00000030>, <0x00000040>,
		<0x00000050>, <0x00000060>,
		<0x00000070>, <0x00000080>,
		<0x00000090>, <0x00000100>,
		<0x00000110>, <0x00000120>,
		<0x00000130>, <0x00000140>,
		<0x00000150>, <0x00000160>,
		<0x00000170>, <0x00000180>,
		<0x00000190>, <0x00000200>,
		<0x00000210>;


		hph_comp_active: hph_comp_active {
		mux {
		pins = "gpio22";
		function = "func1";
		};

		config {
		pins = "gpio22";
		output-high;
		qcom,drive-strength = <8>;
		};
		};

		hph_comp_sleep: hph_comp_sleep {
		mux {
		pins = "gpio22";
		function = "func1";
		};

		config {
		pins = "gpio22";
		qcom,drive-strength = <2>;
		};
		};
		};

Documentation/devicetree/bindings/qdsp/msm-fastrpc.txt

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		@@ -14,6 +14,7 @@ Optional properties:
		- qcom,rpc-latency-us: FastRPC QoS latency vote
		- qcom,adsp-remoteheap-vmid: FastRPC remote heap VMID list
		- qcom,secure-context-bank : Bool indicating secure FastRPC context bank.
		- qcom,fastrpc-legacy-remote-heap : Bool indicating hypervisor is not supported.

		Optional subnodes:
		- qcom,msm_fastrpc_compute_cb : Child nodes representing the compute context