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Commit 38b89761 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "clk: qcom: Add clock measure support for ipa_2x_clk for TRINKET"

parents 409af4b4 1f47a686

drivers/clk/qcom/debugcc-trinket.c

+3 −0
Original line number Original line Diff line number Diff line
@@ -216,6 +216,7 @@ static const char *const debug_mux_parent_names[] = { 
	"gpu_cc_gx_gfx3d_clk",

	"gpu_cc_gx_gfx3d_clk",

	"gpu_cc_sleep_clk",

	"gpu_cc_sleep_clk",

	"measure_only_mccc_clk",

	"measure_only_mccc_clk",

	"measure_only_ipa_2x_clk",

	"video_cc_apb_clk",

	"video_cc_apb_clk",

	"video_cc_at_clk",

	"video_cc_at_clk",

	"video_cc_sleep_clk",

	"video_cc_sleep_clk",
@@ -604,6 +605,8 @@ static struct clk_debug_mux gcc_debug_mux = { 
			0x16, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 },

			0x16, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 },

		{ "measure_only_mccc_clk", 0x97, 1, MC_CC,

		{ "measure_only_mccc_clk", 0x97, 1, MC_CC,

			0x97, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 },

			0x97, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 },

		{ "measure_only_ipa_2x_clk", 0xC2, 1, GCC,

			0xC2, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 },

		{ "video_cc_apb_clk", 0x42, 1, VIDEO_CC,

		{ "video_cc_apb_clk", 0x42, 1, VIDEO_CC,

			0x8, 0x3F, 0, 0x7, 0, 5, 0xA4C, 0xA30, 0xA38 },

			0x8, 0x3F, 0, 0x7, 0, 5, 0xA4C, 0xA30, 0xA38 },

		{ "video_cc_at_clk", 0x42, 1, VIDEO_CC,

		{ "video_cc_at_clk", 0x42, 1, VIDEO_CC,

drivers/clk/qcom/gcc-trinket.c

+10 −0
Original line number Original line Diff line number Diff line
@@ -4193,6 +4193,15 @@ static struct clk_dummy measure_only_mccc_clk = { 
	},

	},

};

};





/* Measure-only clock for gcc_ipa_2x_clk. */

static struct clk_dummy measure_only_ipa_2x_clk = {

	.rrate = 1000,

	.hw.init = &(struct clk_init_data){

		.name = "measure_only_ipa_2x_clk",

		.ops = &clk_dummy_ops,

	},

};



struct clk_hw *gcc_trinket_hws[] = {

struct clk_hw *gcc_trinket_hws[] = {

	[GPLL0_OUT_AUX2] = &gpll0_out_aux2.hw,

	[GPLL0_OUT_AUX2] = &gpll0_out_aux2.hw,

	[GPLL0_OUT_MAIN] = &gpll0_out_main.hw,

	[GPLL0_OUT_MAIN] = &gpll0_out_main.hw,
@@ -4200,6 +4209,7 @@ struct clk_hw *gcc_trinket_hws[] = { 
	[GPLL8_OUT_MAIN] = &gpll8_out_main.hw,

	[GPLL8_OUT_MAIN] = &gpll8_out_main.hw,

	[GPLL9_OUT_MAIN] = &gpll9_out_main.hw,

	[GPLL9_OUT_MAIN] = &gpll9_out_main.hw,

	[MEASURE_ONLY_MMCC_CLK] = &measure_only_mccc_clk.hw,

	[MEASURE_ONLY_MMCC_CLK] = &measure_only_mccc_clk.hw,

	[MEASURE_ONLY_IPA_2X_CLK] = &measure_only_ipa_2x_clk.hw,

};

};





static struct clk_regmap *gcc_trinket_clocks[] = {

static struct clk_regmap *gcc_trinket_clocks[] = {

include/dt-bindings/clock/qcom,gcc-trinket.h

+210 −210
Original line number Original line Diff line number Diff line
@@ -20,216 +20,216 @@ 
#define GPLL8_OUT_MAIN				3

#define GPLL8_OUT_MAIN				3

#define GPLL9_OUT_MAIN				4

#define GPLL9_OUT_MAIN				4

#define MEASURE_ONLY_MMCC_CLK			5

#define MEASURE_ONLY_MMCC_CLK			5

#define GPLL0_OUT_EARLY				6

#define MEASURE_ONLY_IPA_2X_CLK			6

#define GPLL3_OUT_EARLY				7

#define GPLL0_OUT_EARLY				7

#define GPLL4_OUT_MAIN				8

#define GPLL3_OUT_EARLY				8

#define GPLL5_OUT_MAIN				9

#define GPLL4_OUT_MAIN				9

#define GPLL6_OUT_EARLY				10

#define GPLL5_OUT_MAIN				10

#define GPLL7_OUT_MAIN				11

#define GPLL6_OUT_EARLY				11

#define GPLL8_OUT_EARLY				12

#define GPLL7_OUT_MAIN				12

#define GPLL9_OUT_EARLY				13

#define GPLL8_OUT_EARLY				13

#define GCC_AHB2PHY_CSI_CLK			14

#define GPLL9_OUT_EARLY				14

#define GCC_AHB2PHY_USB_CLK			15

#define GCC_AHB2PHY_CSI_CLK			15

#define GCC_APC_VS_CLK				16

#define GCC_AHB2PHY_USB_CLK			16

#define GCC_BOOT_ROM_AHB_CLK			17

#define GCC_APC_VS_CLK				17

#define GCC_CAMERA_AHB_CLK			18

#define GCC_BOOT_ROM_AHB_CLK			18

#define GCC_CAMERA_XO_CLK			19

#define GCC_CAMERA_AHB_CLK			19

#define GCC_CAMSS_AHB_CLK_SRC			20

#define GCC_CAMERA_XO_CLK			20

#define GCC_CAMSS_CCI_AHB_CLK			21

#define GCC_CAMSS_AHB_CLK_SRC			21

#define GCC_CAMSS_CCI_CLK			22

#define GCC_CAMSS_CCI_AHB_CLK			22

#define GCC_CAMSS_CCI_CLK_SRC			23

#define GCC_CAMSS_CCI_CLK			23

#define GCC_CAMSS_CPHY_CSID0_CLK		24

#define GCC_CAMSS_CCI_CLK_SRC			24

#define GCC_CAMSS_CPHY_CSID1_CLK		25

#define GCC_CAMSS_CPHY_CSID0_CLK		25

#define GCC_CAMSS_CPHY_CSID2_CLK		26

#define GCC_CAMSS_CPHY_CSID1_CLK		26

#define GCC_CAMSS_CPHY_CSID3_CLK		27

#define GCC_CAMSS_CPHY_CSID2_CLK		27

#define GCC_CAMSS_CPP_AHB_CLK			28

#define GCC_CAMSS_CPHY_CSID3_CLK		28

#define GCC_CAMSS_CPP_AXI_CLK			29

#define GCC_CAMSS_CPP_AHB_CLK			29

#define GCC_CAMSS_CPP_CLK			30

#define GCC_CAMSS_CPP_AXI_CLK			30

#define GCC_CAMSS_CPP_CLK_SRC			31

#define GCC_CAMSS_CPP_CLK			31

#define GCC_CAMSS_CPP_VBIF_AHB_CLK		32

#define GCC_CAMSS_CPP_CLK_SRC			32

#define GCC_CAMSS_CSI0_AHB_CLK			33

#define GCC_CAMSS_CPP_VBIF_AHB_CLK		33

#define GCC_CAMSS_CSI0_CLK			34

#define GCC_CAMSS_CSI0_AHB_CLK			34

#define GCC_CAMSS_CSI0_CLK_SRC			35

#define GCC_CAMSS_CSI0_CLK			35

#define GCC_CAMSS_CSI0PHYTIMER_CLK		36

#define GCC_CAMSS_CSI0_CLK_SRC			36

#define GCC_CAMSS_CSI0PHYTIMER_CLK_SRC		37

#define GCC_CAMSS_CSI0PHYTIMER_CLK		37

#define GCC_CAMSS_CSI0PIX_CLK			38

#define GCC_CAMSS_CSI0PHYTIMER_CLK_SRC		38

#define GCC_CAMSS_CSI0RDI_CLK			39

#define GCC_CAMSS_CSI0PIX_CLK			39

#define GCC_CAMSS_CSI1_AHB_CLK			40

#define GCC_CAMSS_CSI0RDI_CLK			40

#define GCC_CAMSS_CSI1_CLK			41

#define GCC_CAMSS_CSI1_AHB_CLK			41

#define GCC_CAMSS_CSI1_CLK_SRC			42

#define GCC_CAMSS_CSI1_CLK			42

#define GCC_CAMSS_CSI1PHYTIMER_CLK		43

#define GCC_CAMSS_CSI1_CLK_SRC			43

#define GCC_CAMSS_CSI1PHYTIMER_CLK_SRC		44

#define GCC_CAMSS_CSI1PHYTIMER_CLK		44

#define GCC_CAMSS_CSI1PIX_CLK			45

#define GCC_CAMSS_CSI1PHYTIMER_CLK_SRC		45

#define GCC_CAMSS_CSI1RDI_CLK			46

#define GCC_CAMSS_CSI1PIX_CLK			46

#define GCC_CAMSS_CSI2_AHB_CLK			47

#define GCC_CAMSS_CSI1RDI_CLK			47

#define GCC_CAMSS_CSI2_CLK			48

#define GCC_CAMSS_CSI2_AHB_CLK			48

#define GCC_CAMSS_CSI2_CLK_SRC			49

#define GCC_CAMSS_CSI2_CLK			49

#define GCC_CAMSS_CSI2PHYTIMER_CLK		50

#define GCC_CAMSS_CSI2_CLK_SRC			50

#define GCC_CAMSS_CSI2PHYTIMER_CLK_SRC		51

#define GCC_CAMSS_CSI2PHYTIMER_CLK		51

#define GCC_CAMSS_CSI2PIX_CLK			52

#define GCC_CAMSS_CSI2PHYTIMER_CLK_SRC		52

#define GCC_CAMSS_CSI2RDI_CLK			53

#define GCC_CAMSS_CSI2PIX_CLK			53

#define GCC_CAMSS_CSI3_AHB_CLK			54

#define GCC_CAMSS_CSI2RDI_CLK			54

#define GCC_CAMSS_CSI3_CLK			55

#define GCC_CAMSS_CSI3_AHB_CLK			55

#define GCC_CAMSS_CSI3_CLK_SRC			56

#define GCC_CAMSS_CSI3_CLK			56

#define GCC_CAMSS_CSI3PIX_CLK			57

#define GCC_CAMSS_CSI3_CLK_SRC			57

#define GCC_CAMSS_CSI3RDI_CLK			58

#define GCC_CAMSS_CSI3PIX_CLK			58

#define GCC_CAMSS_CSI_VFE0_CLK			59

#define GCC_CAMSS_CSI3RDI_CLK			59

#define GCC_CAMSS_CSI_VFE1_CLK			60

#define GCC_CAMSS_CSI_VFE0_CLK			60

#define GCC_CAMSS_CSIPHY0_CLK			61

#define GCC_CAMSS_CSI_VFE1_CLK			61

#define GCC_CAMSS_CSIPHY1_CLK			62

#define GCC_CAMSS_CSIPHY0_CLK			62

#define GCC_CAMSS_CSIPHY2_CLK			63

#define GCC_CAMSS_CSIPHY1_CLK			63

#define GCC_CAMSS_CSIPHY3_CLK			64

#define GCC_CAMSS_CSIPHY2_CLK			64

#define GCC_CAMSS_CSIPHY_CLK_SRC		65

#define GCC_CAMSS_CSIPHY3_CLK			65

#define GCC_CAMSS_GP0_CLK			66

#define GCC_CAMSS_CSIPHY_CLK_SRC		66

#define GCC_CAMSS_GP0_CLK_SRC			67

#define GCC_CAMSS_GP0_CLK			67

#define GCC_CAMSS_GP1_CLK			68

#define GCC_CAMSS_GP0_CLK_SRC			68

#define GCC_CAMSS_GP1_CLK_SRC			69

#define GCC_CAMSS_GP1_CLK			69

#define GCC_CAMSS_ISPIF_AHB_CLK			70

#define GCC_CAMSS_GP1_CLK_SRC			70

#define GCC_CAMSS_JPEG_AHB_CLK			71

#define GCC_CAMSS_ISPIF_AHB_CLK			71

#define GCC_CAMSS_JPEG_AXI_CLK			72

#define GCC_CAMSS_JPEG_AHB_CLK			72

#define GCC_CAMSS_JPEG_CLK			73

#define GCC_CAMSS_JPEG_AXI_CLK			73

#define GCC_CAMSS_JPEG_CLK_SRC			74

#define GCC_CAMSS_JPEG_CLK			74

#define GCC_CAMSS_MCLK0_CLK			75

#define GCC_CAMSS_JPEG_CLK_SRC			75

#define GCC_CAMSS_MCLK0_CLK_SRC			76

#define GCC_CAMSS_MCLK0_CLK			76

#define GCC_CAMSS_MCLK1_CLK			77

#define GCC_CAMSS_MCLK0_CLK_SRC			77

#define GCC_CAMSS_MCLK1_CLK_SRC			78

#define GCC_CAMSS_MCLK1_CLK			78

#define GCC_CAMSS_MCLK2_CLK			79

#define GCC_CAMSS_MCLK1_CLK_SRC			79

#define GCC_CAMSS_MCLK2_CLK_SRC			80

#define GCC_CAMSS_MCLK2_CLK			80

#define GCC_CAMSS_MCLK3_CLK			81

#define GCC_CAMSS_MCLK2_CLK_SRC			81

#define GCC_CAMSS_MCLK3_CLK_SRC			82

#define GCC_CAMSS_MCLK3_CLK			82

#define GCC_CAMSS_MICRO_AHB_CLK			83

#define GCC_CAMSS_MCLK3_CLK_SRC			83

#define GCC_CAMSS_THROTTLE_NRT_AXI_CLK		84

#define GCC_CAMSS_MICRO_AHB_CLK			84

#define GCC_CAMSS_THROTTLE_RT_AXI_CLK		85

#define GCC_CAMSS_THROTTLE_NRT_AXI_CLK		85

#define GCC_CAMSS_TOP_AHB_CLK			86

#define GCC_CAMSS_THROTTLE_RT_AXI_CLK		86

#define GCC_CAMSS_VFE0_AHB_CLK			87

#define GCC_CAMSS_TOP_AHB_CLK			87

#define GCC_CAMSS_VFE0_CLK			88

#define GCC_CAMSS_VFE0_AHB_CLK			88

#define GCC_CAMSS_VFE0_CLK_SRC			89

#define GCC_CAMSS_VFE0_CLK			89

#define GCC_CAMSS_VFE0_STREAM_CLK		90

#define GCC_CAMSS_VFE0_CLK_SRC			90

#define GCC_CAMSS_VFE1_AHB_CLK			91

#define GCC_CAMSS_VFE0_STREAM_CLK		91

#define GCC_CAMSS_VFE1_CLK			92

#define GCC_CAMSS_VFE1_AHB_CLK			92

#define GCC_CAMSS_VFE1_CLK_SRC			93

#define GCC_CAMSS_VFE1_CLK			93

#define GCC_CAMSS_VFE1_STREAM_CLK		94

#define GCC_CAMSS_VFE1_CLK_SRC			94

#define GCC_CAMSS_VFE_TSCTR_CLK			95

#define GCC_CAMSS_VFE1_STREAM_CLK		95

#define GCC_CAMSS_VFE_VBIF_AHB_CLK		96

#define GCC_CAMSS_VFE_TSCTR_CLK			96

#define GCC_CAMSS_VFE_VBIF_AXI_CLK		97

#define GCC_CAMSS_VFE_VBIF_AHB_CLK		97

#define GCC_CE1_AHB_CLK				98

#define GCC_CAMSS_VFE_VBIF_AXI_CLK		98

#define GCC_CE1_AXI_CLK				99

#define GCC_CE1_AHB_CLK				99

#define GCC_CE1_CLK				100

#define GCC_CE1_AXI_CLK				100

#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK		101

#define GCC_CE1_CLK				101

#define GCC_CPUSS_AHB_CLK			102

#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK		102

#define GCC_CPUSS_AHB_CLK_SRC			103

#define GCC_CPUSS_AHB_CLK			103

#define GCC_CPUSS_GNOC_CLK			104

#define GCC_CPUSS_AHB_CLK_SRC			104

#define GCC_CPUSS_THROTTLE_CORE_CLK		105

#define GCC_CPUSS_GNOC_CLK			105

#define GCC_CPUSS_THROTTLE_XO_CLK		106

#define GCC_CPUSS_THROTTLE_CORE_CLK		106

#define GCC_DISP_AHB_CLK			107

#define GCC_CPUSS_THROTTLE_XO_CLK		107

#define GCC_DISP_GPLL0_DIV_CLK_SRC		108

#define GCC_DISP_AHB_CLK			108

#define GCC_DISP_HF_AXI_CLK			109

#define GCC_DISP_GPLL0_DIV_CLK_SRC		109

#define GCC_DISP_THROTTLE_CORE_CLK		110

#define GCC_DISP_HF_AXI_CLK			110

#define GCC_DISP_XO_CLK				111

#define GCC_DISP_THROTTLE_CORE_CLK		111

#define GCC_GP1_CLK				112

#define GCC_DISP_XO_CLK				112

#define GCC_GP1_CLK_SRC				113

#define GCC_GP1_CLK				113

#define GCC_GP2_CLK				114

#define GCC_GP1_CLK_SRC				114

#define GCC_GP2_CLK_SRC				115

#define GCC_GP2_CLK				115

#define GCC_GP3_CLK				116

#define GCC_GP2_CLK_SRC				116

#define GCC_GP3_CLK_SRC				117

#define GCC_GP3_CLK				117

#define GCC_GPU_CFG_AHB_CLK			118

#define GCC_GP3_CLK_SRC				118

#define GCC_GPU_GPLL0_CLK_SRC			119

#define GCC_GPU_CFG_AHB_CLK			119

#define GCC_GPU_GPLL0_DIV_CLK_SRC		120

#define GCC_GPU_GPLL0_CLK_SRC			120

#define GCC_GPU_MEMNOC_GFX_CLK			121

#define GCC_GPU_GPLL0_DIV_CLK_SRC		121

#define GCC_GPU_SNOC_DVM_GFX_CLK		122

#define GCC_GPU_MEMNOC_GFX_CLK			122

#define GCC_GPU_THROTTLE_CORE_CLK		123

#define GCC_GPU_SNOC_DVM_GFX_CLK		123

#define GCC_GPU_THROTTLE_XO_CLK			124

#define GCC_GPU_THROTTLE_CORE_CLK		124

#define GCC_MSS_VS_CLK				125

#define GCC_GPU_THROTTLE_XO_CLK			125

#define GCC_PDM2_CLK				126

#define GCC_MSS_VS_CLK				126

#define GCC_PDM2_CLK_SRC			127

#define GCC_PDM2_CLK				127

#define GCC_PDM_AHB_CLK				128

#define GCC_PDM2_CLK_SRC			128

#define GCC_PDM_XO4_CLK				129

#define GCC_PDM_AHB_CLK				129

#define GCC_PRNG_AHB_CLK			130

#define GCC_PDM_XO4_CLK				130

#define GCC_QMIP_CAMERA_NRT_AHB_CLK		131

#define GCC_PRNG_AHB_CLK			131

#define GCC_QMIP_CAMERA_RT_AHB_CLK		132

#define GCC_QMIP_CAMERA_NRT_AHB_CLK		132

#define GCC_QMIP_CPUSS_CFG_AHB_CLK		133

#define GCC_QMIP_CAMERA_RT_AHB_CLK		133

#define GCC_QMIP_DISP_AHB_CLK			134

#define GCC_QMIP_CPUSS_CFG_AHB_CLK		134

#define GCC_QMIP_GPU_CFG_AHB_CLK		135

#define GCC_QMIP_DISP_AHB_CLK			135

#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK		136

#define GCC_QMIP_GPU_CFG_AHB_CLK		136

#define GCC_QUPV3_WRAP0_CORE_2X_CLK		137

#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK		137

#define GCC_QUPV3_WRAP0_CORE_CLK		138

#define GCC_QUPV3_WRAP0_CORE_2X_CLK		138

#define GCC_QUPV3_WRAP0_S0_CLK			139

#define GCC_QUPV3_WRAP0_CORE_CLK		139

#define GCC_QUPV3_WRAP0_S0_CLK_SRC		140

#define GCC_QUPV3_WRAP0_S0_CLK			140

#define GCC_QUPV3_WRAP0_S1_CLK			141

#define GCC_QUPV3_WRAP0_S0_CLK_SRC		141

#define GCC_QUPV3_WRAP0_S1_CLK_SRC		142

#define GCC_QUPV3_WRAP0_S1_CLK			142

#define GCC_QUPV3_WRAP0_S2_CLK			143

#define GCC_QUPV3_WRAP0_S1_CLK_SRC		143

#define GCC_QUPV3_WRAP0_S2_CLK_SRC		144

#define GCC_QUPV3_WRAP0_S2_CLK			144

#define GCC_QUPV3_WRAP0_S3_CLK			145

#define GCC_QUPV3_WRAP0_S2_CLK_SRC		145

#define GCC_QUPV3_WRAP0_S3_CLK_SRC		146

#define GCC_QUPV3_WRAP0_S3_CLK			146

#define GCC_QUPV3_WRAP0_S4_CLK			147

#define GCC_QUPV3_WRAP0_S3_CLK_SRC		147

#define GCC_QUPV3_WRAP0_S4_CLK_SRC		148

#define GCC_QUPV3_WRAP0_S4_CLK			148

#define GCC_QUPV3_WRAP0_S5_CLK			149

#define GCC_QUPV3_WRAP0_S4_CLK_SRC		149

#define GCC_QUPV3_WRAP0_S5_CLK_SRC		150

#define GCC_QUPV3_WRAP0_S5_CLK			150

#define GCC_QUPV3_WRAP1_CORE_2X_CLK		151

#define GCC_QUPV3_WRAP0_S5_CLK_SRC		151

#define GCC_QUPV3_WRAP1_CORE_CLK		152

#define GCC_QUPV3_WRAP1_CORE_2X_CLK		152

#define GCC_QUPV3_WRAP1_S0_CLK			153

#define GCC_QUPV3_WRAP1_CORE_CLK		153

#define GCC_QUPV3_WRAP1_S0_CLK_SRC		154

#define GCC_QUPV3_WRAP1_S0_CLK			154

#define GCC_QUPV3_WRAP1_S1_CLK			155

#define GCC_QUPV3_WRAP1_S0_CLK_SRC		155

#define GCC_QUPV3_WRAP1_S1_CLK_SRC		156

#define GCC_QUPV3_WRAP1_S1_CLK			156

#define GCC_QUPV3_WRAP1_S2_CLK			157

#define GCC_QUPV3_WRAP1_S1_CLK_SRC		157

#define GCC_QUPV3_WRAP1_S2_CLK_SRC		158

#define GCC_QUPV3_WRAP1_S2_CLK			158

#define GCC_QUPV3_WRAP1_S3_CLK			159

#define GCC_QUPV3_WRAP1_S2_CLK_SRC		159

#define GCC_QUPV3_WRAP1_S3_CLK_SRC		160

#define GCC_QUPV3_WRAP1_S3_CLK			160

#define GCC_QUPV3_WRAP1_S4_CLK			161

#define GCC_QUPV3_WRAP1_S3_CLK_SRC		161

#define GCC_QUPV3_WRAP1_S4_CLK_SRC		162

#define GCC_QUPV3_WRAP1_S4_CLK			162

#define GCC_QUPV3_WRAP1_S5_CLK			163

#define GCC_QUPV3_WRAP1_S4_CLK_SRC		163

#define GCC_QUPV3_WRAP1_S5_CLK_SRC		164

#define GCC_QUPV3_WRAP1_S5_CLK			164

#define GCC_QUPV3_WRAP_0_M_AHB_CLK		165

#define GCC_QUPV3_WRAP1_S5_CLK_SRC		165

#define GCC_QUPV3_WRAP_0_S_AHB_CLK		166

#define GCC_QUPV3_WRAP_0_M_AHB_CLK		166

#define GCC_QUPV3_WRAP_1_M_AHB_CLK		167

#define GCC_QUPV3_WRAP_0_S_AHB_CLK		167

#define GCC_QUPV3_WRAP_1_S_AHB_CLK		168

#define GCC_QUPV3_WRAP_1_M_AHB_CLK		168

#define GCC_SDCC1_AHB_CLK			169

#define GCC_QUPV3_WRAP_1_S_AHB_CLK		169

#define GCC_SDCC1_APPS_CLK			170

#define GCC_SDCC1_AHB_CLK			170

#define GCC_SDCC1_APPS_CLK_SRC			171

#define GCC_SDCC1_APPS_CLK			171

#define GCC_SDCC1_ICE_CORE_CLK			172

#define GCC_SDCC1_APPS_CLK_SRC			172

#define GCC_SDCC1_ICE_CORE_CLK_SRC		173

#define GCC_SDCC1_ICE_CORE_CLK			173

#define GCC_SDCC2_AHB_CLK			174

#define GCC_SDCC1_ICE_CORE_CLK_SRC		174

#define GCC_SDCC2_APPS_CLK			175

#define GCC_SDCC2_AHB_CLK			175

#define GCC_SDCC2_APPS_CLK_SRC			176

#define GCC_SDCC2_APPS_CLK			176

#define GCC_SYS_NOC_CPUSS_AHB_CLK		177

#define GCC_SDCC2_APPS_CLK_SRC			177

#define GCC_SYS_NOC_UFS_PHY_AXI_CLK		178

#define GCC_SYS_NOC_CPUSS_AHB_CLK		178

#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK		179

#define GCC_SYS_NOC_UFS_PHY_AXI_CLK		179

#define GCC_UFS_PHY_AHB_CLK			180

#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK		180

#define GCC_UFS_PHY_AXI_CLK			181

#define GCC_UFS_PHY_AHB_CLK			181

#define GCC_UFS_PHY_AXI_CLK_SRC			182

#define GCC_UFS_PHY_AXI_CLK			182

#define GCC_UFS_PHY_ICE_CORE_CLK		183

#define GCC_UFS_PHY_AXI_CLK_SRC			183

#define GCC_UFS_PHY_ICE_CORE_CLK_SRC		184

#define GCC_UFS_PHY_ICE_CORE_CLK		184

#define GCC_UFS_PHY_PHY_AUX_CLK			185

#define GCC_UFS_PHY_ICE_CORE_CLK_SRC		185

#define GCC_UFS_PHY_PHY_AUX_CLK_SRC		186

#define GCC_UFS_PHY_PHY_AUX_CLK			186

#define GCC_UFS_PHY_RX_SYMBOL_0_CLK		187

#define GCC_UFS_PHY_PHY_AUX_CLK_SRC		187

#define GCC_UFS_PHY_TX_SYMBOL_0_CLK		188

#define GCC_UFS_PHY_RX_SYMBOL_0_CLK		188

#define GCC_UFS_PHY_UNIPRO_CORE_CLK		189

#define GCC_UFS_PHY_TX_SYMBOL_0_CLK		189

#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC		190

#define GCC_UFS_PHY_UNIPRO_CORE_CLK		190

#define GCC_USB30_PRIM_MASTER_CLK		191

#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC		191

#define GCC_USB30_PRIM_MASTER_CLK_SRC		192

#define GCC_USB30_PRIM_MASTER_CLK		192

#define GCC_USB30_PRIM_MOCK_UTMI_CLK		193

#define GCC_USB30_PRIM_MASTER_CLK_SRC		193

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC	194

#define GCC_USB30_PRIM_MOCK_UTMI_CLK		194

#define GCC_USB30_PRIM_SLEEP_CLK		195

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC	195

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC		196

#define GCC_USB30_PRIM_SLEEP_CLK		196

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK		197

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC		197

#define GCC_USB3_PRIM_PHY_PIPE_CLK		198

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK		198

#define GCC_VDDA_VS_CLK				199

#define GCC_USB3_PRIM_PHY_PIPE_CLK		199

#define GCC_VDDCX_VS_CLK			200

#define GCC_VDDA_VS_CLK				200

#define GCC_VDDMX_VS_CLK			201

#define GCC_VDDCX_VS_CLK			201

#define GCC_VIDEO_AHB_CLK			202

#define GCC_VDDMX_VS_CLK			202

#define GCC_VIDEO_AXI0_CLK			203

#define GCC_VIDEO_AHB_CLK			203

#define GCC_VIDEO_THROTTLE_CORE_CLK		204

#define GCC_VIDEO_AXI0_CLK			204

#define GCC_VIDEO_XO_CLK			205

#define GCC_VIDEO_THROTTLE_CORE_CLK		205

#define GCC_VS_CTRL_AHB_CLK			206

#define GCC_VIDEO_XO_CLK			206

#define GCC_VS_CTRL_CLK				207

#define GCC_VS_CTRL_AHB_CLK			207

#define GCC_VS_CTRL_CLK_SRC			208

#define GCC_VS_CTRL_CLK				208

#define GCC_VSENSOR_CLK_SRC			209

#define GCC_VS_CTRL_CLK_SRC			209

#define GCC_WCSS_VS_CLK				210

#define GCC_VSENSOR_CLK_SRC			210

#define GCC_USB3_PRIM_CLKREF_CLK		211

#define GCC_WCSS_VS_CLK				211

#define GCC_SYS_NOC_COMPUTE_SF_AXI_CLK		212

#define GCC_USB3_PRIM_CLKREF_CLK		212

#define GCC_BIMC_GPU_AXI_CLK			213

#define GCC_SYS_NOC_COMPUTE_SF_AXI_CLK		213

#define GCC_UFS_MEM_CLKREF_CLK			214

#define GCC_BIMC_GPU_AXI_CLK			214



#define GCC_UFS_MEM_CLKREF_CLK			215





/* GCC Resets */

/* GCC Resets */

#define GCC_QUSB2PHY_PRIM_BCR			0

#define GCC_QUSB2PHY_PRIM_BCR			0