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Commit 38320181 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'sunxi-clk-for-4.10' of... 

Merge tag 'sunxi-clk-for-4.10' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next

Pull Allwinner clock changes from Maxime Ripard:

The usual patches from us, but most notably the introduction of the A64
clocks unit.

* tag 'sunxi-clk-for-4.10' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
  clk: sunxi-ng: sun8i-h3: Set CLK_SET_RATE_PARENT for audio module clocks
  clk: sunxi-ng: sun8i-a23: Set CLK_SET_RATE_PARENT for audio module clocks
  clk: sunxi-ng: Add A64 clocks
  clk: sunxi-ng: Implement minimum for multipliers
  clk: sunxi-ng: Add minimums for all the relevant structures and clocks
  clk: sunxi-ng: Finish to convert to structures for arguments
  clk: sunxi-ng: Remove the use of rational computations
  clk: sunxi-ng: Rename the internal structures
  clk: sunxi: mod0: improve function-level documentation
parents c284a7ba 0f6f9302

Documentation/devicetree/bindings/clock/sunxi-ccu.txt

+1 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ Required properties : 
		- "allwinner,sun8i-a23-ccu"

		- "allwinner,sun8i-a33-ccu"

		- "allwinner,sun8i-h3-ccu"

		- "allwinner,sun50i-a64-ccu"



- reg: Must contain the registers base address and length

- clocks: phandle to the oscillators feeding the CCU. Two are needed:

drivers/clk/sunxi-ng/Kconfig

+11 −3
Original line number Diff line number Diff line
@@ -35,17 +35,14 @@ config SUNXI_CCU_NK 


config SUNXI_CCU_NKM

	bool

	select RATIONAL

	select SUNXI_CCU_GATE



config SUNXI_CCU_NKMP

	bool

	select RATIONAL

	select SUNXI_CCU_GATE



config SUNXI_CCU_NM

	bool

	select RATIONAL

	select SUNXI_CCU_FRAC

	select SUNXI_CCU_GATE
@@ -56,6 +53,17 @@ config SUNXI_CCU_MP 


# SoC Drivers



config SUN50I_A64_CCU

	bool "Support for the Allwinner A64 CCU"

	select SUNXI_CCU_DIV

	select SUNXI_CCU_NK

	select SUNXI_CCU_NKM

	select SUNXI_CCU_NKMP

	select SUNXI_CCU_NM

	select SUNXI_CCU_MP

	select SUNXI_CCU_PHASE

	default ARM64 && ARCH_SUNXI



config SUN6I_A31_CCU

	bool "Support for the Allwinner A31/A31s CCU"

	select SUNXI_CCU_DIV

drivers/clk/sunxi-ng/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ obj-$(CONFIG_SUNXI_CCU_NM) += ccu_nm.o 
obj-$(CONFIG_SUNXI_CCU_MP)	+= ccu_mp.o



# SoC support

obj-$(CONFIG_SUN50I_A64_CCU)	+= ccu-sun50i-a64.o

obj-$(CONFIG_SUN6I_A31_CCU)	+= ccu-sun6i-a31.o

obj-$(CONFIG_SUN8I_A23_CCU)	+= ccu-sun8i-a23.o

obj-$(CONFIG_SUN8I_A33_CCU)	+= ccu-sun8i-a33.o

drivers/clk/sunxi-ng/ccu-sun50i-a64.c

0 → 100644
+915 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/clk/sunxi-ng/ccu-sun50i-a64.h

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+72 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2016 Maxime Ripard

 *

 * Maxime Ripard <maxime.ripard@free-electrons.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef _CCU_SUN50I_A64_H_

#define _CCU_SUN50I_A64_H_



#include <dt-bindings/clock/sun50i-a64-ccu.h>

#include <dt-bindings/reset/sun50i-a64-ccu.h>



#define CLK_OSC_12M			0

#define CLK_PLL_CPUX			1

#define CLK_PLL_AUDIO_BASE		2

#define CLK_PLL_AUDIO			3

#define CLK_PLL_AUDIO_2X		4

#define CLK_PLL_AUDIO_4X		5

#define CLK_PLL_AUDIO_8X		6

#define CLK_PLL_VIDEO0			7

#define CLK_PLL_VIDEO0_2X		8

#define CLK_PLL_VE			9

#define CLK_PLL_DDR0			10

#define CLK_PLL_PERIPH0			11

#define CLK_PLL_PERIPH0_2X		12

#define CLK_PLL_PERIPH1			13

#define CLK_PLL_PERIPH1_2X		14

#define CLK_PLL_VIDEO1			15

#define CLK_PLL_GPU			16

#define CLK_PLL_MIPI			17

#define CLK_PLL_HSIC			18

#define CLK_PLL_DE			19

#define CLK_PLL_DDR1			20

#define CLK_CPUX			21

#define CLK_AXI				22

#define CLK_APB				23

#define CLK_AHB1			24

#define CLK_APB1			25

#define CLK_APB2			26

#define CLK_AHB2			27



/* All the bus gates are exported */



/* The first bunch of module clocks are exported */



#define CLK_USB_OHCI0_12M		90



#define CLK_USB_OHCI1_12M		92



#define CLK_DRAM			94



/* All the DRAM gates are exported */



/* Some more module clocks are exported */



#define CLK_MBUS			112



/* And the DSI and GPU module clock is exported */



#define CLK_NUMBER			(CLK_GPU + 1)



#endif /* _CCU_SUN50I_A64_H_ */