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Commit 381b943b authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Remove i915_address_space.start 



Once upon a time, back in the UMS days, we supported userspace
initialising the GTT and sharing portions of the GTT with other users.
Now, we own the GTT (both global and per-process) and the tables always
start at 0 - so we can remove i915_address_space.start and forget about
this old complication.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarMatthew Auld <matthew.auld@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170215084357.19977-20-chris@chris-wilson.co.uk
parent 998f6c00

drivers/gpu/drm/i915/i915_debugfs.c

+1 −1
Original line number Diff line number Diff line
@@ -476,7 +476,7 @@ static int i915_gem_object_info(struct seq_file *m, void *data) 
		   dpy_count, dpy_size);



	seq_printf(m, "%llu [%llu] gtt total\n",

		   ggtt->base.total, ggtt->mappable_end - ggtt->base.start);

		   ggtt->base.total, ggtt->mappable_end);



	seq_putc(m, '\n');

	print_batch_pool_stats(m, dev_priv);

drivers/gpu/drm/i915/i915_gem_evict.c

+1 −1
Original line number Diff line number Diff line
@@ -274,7 +274,7 @@ int i915_gem_evict_for_node(struct i915_address_space *vm, 
	check_color = vm->mm.color_adjust;

	if (check_color) {

		/* Expand search to cover neighbouring guard pages (or lack!) */

		if (start > vm->start)

		if (start)

			start -= I915_GTT_PAGE_SIZE;



		/* Always look at the page afterwards to avoid the end-of-GTT */

drivers/gpu/drm/i915/i915_gem_gtt.c

+6 −10
Original line number Diff line number Diff line
@@ -1218,10 +1218,9 @@ static void gen8_dump_pdp(struct i915_hw_ppgtt *ppgtt, 
static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)

{

	struct i915_address_space *vm = &ppgtt->base;

	uint64_t start = ppgtt->base.start;

	uint64_t length = ppgtt->base.total;

	const gen8_pte_t scratch_pte =

		gen8_pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC);

	u64 start = 0, length = ppgtt->base.total;



	if (!USES_FULL_48BIT_PPGTT(vm->i915)) {

		gen8_dump_pdp(ppgtt, &ppgtt->pdp, start, length, scratch_pte, m);
@@ -1288,7 +1287,6 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) 
	if (ret)

		return ret;



	ppgtt->base.start = 0;

	ppgtt->base.cleanup = gen8_ppgtt_cleanup;

	ppgtt->base.unbind_vma = ppgtt_unbind_vma;

	ppgtt->base.bind_vma = ppgtt_bind_vma;
@@ -1349,9 +1347,8 @@ static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) 
	struct i915_address_space *vm = &ppgtt->base;

	struct i915_page_table *unused;

	gen6_pte_t scratch_pte;

	uint32_t pd_entry;

	uint32_t  pte, pde;

	uint32_t start = ppgtt->base.start, length = ppgtt->base.total;

	u32 pd_entry, pte, pde;

	u32 start = 0, length = ppgtt->base.total;



	scratch_pte = vm->pte_encode(vm->scratch_page.daddr,

				     I915_CACHE_LLC, 0);
@@ -1785,7 +1782,6 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) 
	ppgtt->base.unbind_vma = ppgtt_unbind_vma;

	ppgtt->base.bind_vma = ppgtt_bind_vma;

	ppgtt->base.cleanup = gen6_ppgtt_cleanup;

	ppgtt->base.start = 0;

	ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE;

	ppgtt->debug_dump = gen6_dump_ppgtt;
@@ -1826,7 +1822,7 @@ static void i915_address_space_init(struct i915_address_space *vm, 
{

	i915_gem_timeline_init(dev_priv, &vm->timeline, name);



	drm_mm_init(&vm->mm, vm->start, vm->total);

	drm_mm_init(&vm->mm, 0, vm->total);

	vm->mm.head_node.color = I915_COLOR_UNEVICTABLE;



	INIT_LIST_HEAD(&vm->active_list);
@@ -2012,7 +2008,7 @@ void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv) 


	i915_check_and_clear_faults(dev_priv);



	ggtt->base.clear_range(&ggtt->base, ggtt->base.start, ggtt->base.total);

	ggtt->base.clear_range(&ggtt->base, 0, ggtt->base.total);



	i915_ggtt_invalidate(dev_priv);

}
@@ -2980,7 +2976,7 @@ void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv) 
	i915_check_and_clear_faults(dev_priv);



	/* First fill our portion of the GTT with scratch pages */

	ggtt->base.clear_range(&ggtt->base, ggtt->base.start, ggtt->base.total);

	ggtt->base.clear_range(&ggtt->base, 0, ggtt->base.total);



	ggtt->base.closed = true; /* skip rewriting PTE on VMA unbind */

drivers/gpu/drm/i915/i915_gem_gtt.h

+0 −1
Original line number Diff line number Diff line
@@ -256,7 +256,6 @@ struct i915_address_space { 
	 */

	struct drm_i915_file_private *file;

	struct list_head global_link;

	u64 start;		/* Start offset always 0 for dri2 */

	u64 total;		/* size addr space maps (ex. 2GB for ggtt) */



	bool closed;

drivers/gpu/drm/i915/i915_vgpu.c

+4 −5
Original line number Diff line number Diff line
@@ -179,7 +179,7 @@ static int vgt_balloon_space(struct i915_ggtt *ggtt, 
int intel_vgt_balloon(struct drm_i915_private *dev_priv)

{

	struct i915_ggtt *ggtt = &dev_priv->ggtt;

	unsigned long ggtt_end = ggtt->base.start + ggtt->base.total;

	unsigned long ggtt_end = ggtt->base.total;



	unsigned long mappable_base, mappable_size, mappable_end;

	unsigned long unmappable_base, unmappable_size, unmappable_end;
@@ -202,8 +202,7 @@ int intel_vgt_balloon(struct drm_i915_private *dev_priv) 
	DRM_INFO("Unmappable graphic memory: base 0x%lx size %ldKiB\n",

		 unmappable_base, unmappable_size / 1024);



	if (mappable_base < ggtt->base.start ||

	    mappable_end > ggtt->mappable_end ||

	if (mappable_end > ggtt->mappable_end ||

	    unmappable_base < ggtt->mappable_end ||

	    unmappable_end > ggtt_end) {

		DRM_ERROR("Invalid ballooning configuration!\n");
@@ -231,9 +230,9 @@ int intel_vgt_balloon(struct drm_i915_private *dev_priv) 
	}



	/* Mappable graphic memory ballooning */

	if (mappable_base > ggtt->base.start) {

	if (mappable_base) {

		ret = vgt_balloon_space(ggtt, &bl_info.space[0],

					ggtt->base.start, mappable_base);

					0, mappable_base);



		if (ret)

			goto err;