Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 37ab3662 authored by Mikko Perttunen's avatar Mikko Perttunen Committed by Peter De Schrijver
Browse files

clk: tegra: Enable hardware control of SATA PLL 



This makes the SATA PLL be controlled by hardware instead of software.
This is required for working SATA support.

Signed-off-by: default avatarMikko Perttunen <mperttunen@nvidia.com>
Acked-by: default avatarStephen Warren <swarren@nvidia.com>
parent 167d5366

drivers/clk/tegra/clk-pll.c

+8 −0
Original line number Diff line number Diff line
@@ -110,6 +110,9 @@ 
#define XUSBIO_PLL_CFG0_SEQ_ENABLE		BIT(24)

#define XUSBIO_PLL_CFG0_SEQ_START_STATE		BIT(25)



#define SATA_PLL_CFG0		0x490

#define SATA_PLL_CFG0_PADPLL_RESET_SWCTL	BIT(0)



#define PLLE_MISC_PLLE_PTS	BIT(8)

#define PLLE_MISC_IDDQ_SW_VALUE	BIT(13)

#define PLLE_MISC_IDDQ_SW_CTRL	BIT(14)
@@ -1361,6 +1364,11 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw) 
	val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;

	pll_writel(val, XUSBIO_PLL_CFG0, pll);



	/* Enable hw control of SATA pll */

	val = pll_readl(SATA_PLL_CFG0, pll);

	val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;

	pll_writel(val, SATA_PLL_CFG0, pll);



out:

	if (pll->lock)

		spin_unlock_irqrestore(pll->lock, flags);