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Commit 37903009 authored by Abhijit Pagare's avatar Abhijit Pagare Committed by Paul Walmsley
Browse files

ARM: OMAP4: PM: OMAP4 Power Domain Porting Related Clean-up. 



Module offsets were same for OMAP2 and OMAP3 while they differ for OMAP4.
Hence we need different macros for identifying platform specific offsets.

Signed-off-by: default avatarAbhijit Pagare <abhijitpagare@ti.com>
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
parent c6a6e6e2

arch/arm/mach-omap2/clockdomain.c

+2 −2
Original line number Diff line number Diff line
@@ -413,7 +413,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm) 
	if (cpu_is_omap24xx()) {



		cm_set_mod_reg_bits(OMAP24XX_FORCESTATE,

				    clkdm->pwrdm.ptr->prcm_offs, PM_PWSTCTRL);

			    clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);



	} else if (cpu_is_omap34xx()) {
@@ -455,7 +455,7 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm) 
	if (cpu_is_omap24xx()) {



		cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE,

				      clkdm->pwrdm.ptr->prcm_offs, PM_PWSTCTRL);

			      clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);



	} else if (cpu_is_omap34xx()) {

arch/arm/mach-omap2/pm-debug.c

+7 −7
Original line number Diff line number Diff line
@@ -68,8 +68,8 @@ void omap2_pm_dump(int mode, int resume, unsigned int us) 
		/* MPU */

		DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET);

		DUMP_CM_MOD_REG(MPU_MOD, CM_CLKSTCTRL);

		DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTCTRL);

		DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTST);

		DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTCTRL);

		DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTST);

		DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP);

#endif

#if 0
@@ -93,7 +93,7 @@ void omap2_pm_dump(int mode, int resume, unsigned int us) 
		DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN);

		DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN);

		DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE);

		DUMP_PRM_MOD_REG(CORE_MOD, PM_PWSTST);

		DUMP_PRM_MOD_REG(CORE_MOD, OMAP2_PM_PWSTST);

#endif

#if 0

		/* DSP */
@@ -104,10 +104,10 @@ void omap2_pm_dump(int mode, int resume, unsigned int us) 
			DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE);

			DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL);

			DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSTCTRL);

			DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTCTRL);

			DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTST);

			DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTCTRL);

			DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTST);

			DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTCTRL);

			DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTST);

			DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_PM_PWSTCTRL);

			DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_PM_PWSTST);

		}

#endif

	} else {

arch/arm/mach-omap2/pm24xx.c

+3 −2
Original line number Diff line number Diff line
@@ -219,11 +219,12 @@ static void omap2_enter_mpu_retention(void) 
		/* Try to enter MPU retention */

		prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |

				  OMAP_LOGICRETSTATE,

				  MPU_MOD, PM_PWSTCTRL);

				  MPU_MOD, OMAP2_PM_PWSTCTRL);

	} else {

		/* Block MPU retention */



		prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, PM_PWSTCTRL);

		prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD,

						 OMAP2_PM_PWSTCTRL);

		only_idle = 1;

	}

arch/arm/mach-omap2/pm34xx.c

+12 −12
Original line number Diff line number Diff line
@@ -685,7 +685,7 @@ static void __init omap3_iva_idle(void) 
	prm_write_mod_reg(OMAP3430_RST1_IVA2 |

			  OMAP3430_RST2_IVA2 |

			  OMAP3430_RST3_IVA2,

			  OMAP3430_IVA2_MOD, RM_RSTCTRL);

			  OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);



	/* Enable IVA2 clock */

	cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2,
@@ -696,7 +696,7 @@ static void __init omap3_iva_idle(void) 
			 OMAP343X_CONTROL_IVA2_BOOTMOD);



	/* Un-reset IVA2 */

	prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL);

	prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);



	/* Disable IVA2 clock */

	cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
@@ -705,7 +705,7 @@ static void __init omap3_iva_idle(void) 
	prm_write_mod_reg(OMAP3430_RST1_IVA2 |

			  OMAP3430_RST2_IVA2 |

			  OMAP3430_RST3_IVA2,

			  OMAP3430_IVA2_MOD, RM_RSTCTRL);

			  OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);

}



static void __init omap3_d2d_idle(void)
@@ -728,8 +728,8 @@ static void __init omap3_d2d_idle(void) 
	/* reset modem */

	prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON |

			  OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST,

			  CORE_MOD, RM_RSTCTRL);

	prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL);

			  CORE_MOD, OMAP2_RM_RSTCTRL);

	prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);

}



static void __init prcm_setup_regs(void)
@@ -916,13 +916,13 @@ static void __init prcm_setup_regs(void) 
	prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);



	/* Clear any pending 'reset' flags */

	prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);

	prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);

	prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);

	prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);

	prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);

	prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);

	prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);

	prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);

	prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);

	prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);

	prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);

	prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);

	prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);

	prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);



	/* Clear any pending PRCM interrupts */

	prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);

arch/arm/mach-omap2/powerdomain.c

+11 −11
Original line number Diff line number Diff line
@@ -710,7 +710,7 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) 


	prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,

			     (pwrst << OMAP_POWERSTATE_SHIFT),

			     pwrdm->prcm_offs, PM_PWSTCTRL);

			     pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);



	return 0;

}
@@ -728,7 +728,7 @@ int pwrdm_read_next_pwrst(struct powerdomain *pwrdm) 
	if (!pwrdm)

		return -EINVAL;



	return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTCTRL,

	return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL,

					OMAP_POWERSTATE_MASK);

}
@@ -745,7 +745,7 @@ int pwrdm_read_pwrst(struct powerdomain *pwrdm) 
	if (!pwrdm)

		return -EINVAL;



	return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTST,

	return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST,

					OMAP_POWERSTATEST_MASK);

}
@@ -796,7 +796,7 @@ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) 
	 */

	prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE,

			     (pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE)),

			     pwrdm->prcm_offs, PM_PWSTCTRL);

			     pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);



	return 0;

}
@@ -856,7 +856,7 @@ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) 
	}



	prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)),

			     pwrdm->prcm_offs, PM_PWSTCTRL);

			     pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);



	return 0;

}
@@ -917,7 +917,7 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) 
	}



	prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,

			     PM_PWSTCTRL);

			     OMAP2_PM_PWSTCTRL);



	return 0;

}
@@ -936,7 +936,7 @@ int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) 
	if (!pwrdm)

		return -EINVAL;



	return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTST,

	return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST,

					OMAP3430_LOGICSTATEST);

}
@@ -1010,7 +1010,7 @@ int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) 
		return -EEXIST;

	}



	return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTST, m);

	return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST, m);

}



/**
@@ -1114,7 +1114,7 @@ int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm) 
		 pwrdm->name);



	prm_rmw_mod_reg_bits(0, 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,

			     pwrdm->prcm_offs, PM_PWSTCTRL);

			     pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);



	return 0;

}
@@ -1142,7 +1142,7 @@ int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm) 
		 pwrdm->name);



	prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, 0,

			     pwrdm->prcm_offs, PM_PWSTCTRL);

			     pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);



	return 0;

}
@@ -1183,7 +1183,7 @@ int pwrdm_wait_transition(struct powerdomain *pwrdm) 
	 */



	/* XXX Is this udelay() value meaningful? */

	while ((prm_read_mod_reg(pwrdm->prcm_offs, PM_PWSTST) &

	while ((prm_read_mod_reg(pwrdm->prcm_offs, OMAP2_PM_PWSTST) &

		OMAP_INTRANSITION) &&

	       (c++ < PWRDM_TRANSITION_BAILOUT))

		udelay(1);