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Commit 3757b946 authored by Naveen Yadav's avatar Naveen Yadav
Browse files

clk: qcom: cpu: Set the latch interface bypass bit for lucid PLL 



In lucid pll when slew is not supported the LATCH_INTERFACE_BYPASS
bit of USER_CTL_U register needs to set in order to configure the PLL.
Add support for the same.

Change-Id: Icc3ef45367737692ba8537e1c43a3756b22fe842
Signed-off-by: default avatarNaveen Yadav <naveenky@codeaurora.org>
parent d8ccfa1e

drivers/clk/qcom/clk-cpu-sdxprairie.c

+3 −1
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -750,6 +750,8 @@ static int __init cpu_clock_init(void) 
		l_val =  readl_relaxed(base + LUCID_PLL_OFF_L_VAL);

	}



	writel_relaxed(0xC05, base + LUCID_PLL_OFF_USER_CTL_U);



	cpucc_clk_init_rate = l_val * XO_RATE;



	regval = readl_relaxed(base);