davinci: DA8xx: CFGCHIP2 register definitions

#define DA8XX_SYSCFG_BASE	(IO_PHYS + 0x14000)

#define DA8XX_SYSCFG_VIRT(x)	(da8xx_syscfg_base + (x))

#define DA8XX_JTAG_ID_REG	0x18

#define DA8XX_CFGCHIP2_REG	0x184

#define DA8XX_CFGCHIP3_REG	0x188

#define DA8XX_PSC0_BASE		0x01c10000

/*

 * USB related definitions

 *

 * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>

 *

 * This file is licensed under the terms of the GNU General Public License

 * version 2. This program is licensed "as is" without any warranty of any

 * kind, whether express or implied.

 */

#ifndef __ASM_ARCH_USB_H

#define __ASM_ARCH_USB_H

/* DA8xx CFGCHIP2 (USB 2.0 PHY Control) register bits */

#define CFGCHIP2_PHYCLKGD	(1 << 17)

#define CFGCHIP2_VBUSSENSE	(1 << 16)

#define CFGCHIP2_RESET		(1 << 15)

#define CFGCHIP2_OTGMODE	(3 << 13)

#define CFGCHIP2_NO_OVERRIDE	(0 << 13)

#define CFGCHIP2_FORCE_HOST	(1 << 13)

#define CFGCHIP2_FORCE_DEVICE 	(2 << 13)

#define CFGCHIP2_FORCE_HOST_VBUS_LOW (3 << 13)

#define CFGCHIP2_USB1PHYCLKMUX	(1 << 12)

#define CFGCHIP2_USB2PHYCLKMUX	(1 << 11)

#define CFGCHIP2_PHYPWRDN	(1 << 10)

#define CFGCHIP2_OTGPWRDN	(1 << 9)

#define CFGCHIP2_DATPOL 	(1 << 8)

#define CFGCHIP2_USB1SUSPENDM	(1 << 7)

#define CFGCHIP2_PHY_PLLON	(1 << 6)	/* override PLL suspend */

#define CFGCHIP2_SESENDEN	(1 << 5)	/* Vsess_end comparator */

#define CFGCHIP2_VBDTCTEN	(1 << 4)	/* Vbus comparator */

#define CFGCHIP2_REFFREQ	(0xf << 0)

#define CFGCHIP2_REFFREQ_12MHZ	(1 << 0)

#define CFGCHIP2_REFFREQ_24MHZ	(2 << 0)

#define CFGCHIP2_REFFREQ_48MHZ	(3 << 0)

#endif	/* ifndef __ASM_ARCH_USB_H */