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Commit 36b2a8d5 authored by Stephane Eranian's avatar Stephane Eranian Committed by Andi Kleen
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[PATCH] x86-64: add X86_FEATURE_PEBS and detection 



Here is a patch (used by perfmon2) to detect the presence of the
Precise Event Based Sampling (PEBS) feature for Intel 64-bit processors.
The patch also adds the cpu_has_pebs macro.

changelog:
	- adds X86_FEATURE_PEBS
	- adds cpu_has_pebs to test for X86_FEATURE_PEBS

Signed-off-by: default avatarstephane eranian <eranian@hpl.hp.com>
Signed-off-by: default avatarAndi Kleen <ak@suse.de>
parent bd1d5995

arch/x86_64/kernel/setup.c

+7 −0
Original line number Original line Diff line number Diff line
@@ -835,6 +835,13 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c) 
			set_bit(X86_FEATURE_ARCH_PERFMON, &c->x86_capability);

			set_bit(X86_FEATURE_ARCH_PERFMON, &c->x86_capability);

	}

	}





	if (cpu_has_ds) {

		unsigned int l1, l2;

		rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);

		if (!(l1 & (1<<12)))

			set_bit(X86_FEATURE_PEBS, c->x86_capability);

	}



	n = c->extended_cpuid_level;

	n = c->extended_cpuid_level;

	if (n >= 0x80000008) {

	if (n >= 0x80000008) {

		unsigned eax = cpuid_eax(0x80000008);

		unsigned eax = cpuid_eax(0x80000008);

include/asm-x86_64/cpufeature.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -68,6 +68,7 @@ 
#define X86_FEATURE_FXSAVE_LEAK (3*32+7)  /* FIP/FOP/FDP leaks through FXSAVE */

#define X86_FEATURE_FXSAVE_LEAK (3*32+7)  /* FIP/FOP/FDP leaks through FXSAVE */

#define X86_FEATURE_UP		(3*32+8) /* SMP kernel running on UP */

#define X86_FEATURE_UP		(3*32+8) /* SMP kernel running on UP */

#define X86_FEATURE_ARCH_PERFMON (3*32+9) /* Intel Architectural PerfMon */

#define X86_FEATURE_ARCH_PERFMON (3*32+9) /* Intel Architectural PerfMon */

#define X86_FEATURE_PEBS	(3*32+10) /* Precise-Event Based Sampling */





/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */

/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */

#define X86_FEATURE_XMM3	(4*32+ 0) /* Streaming SIMD Extensions-3 */

#define X86_FEATURE_XMM3	(4*32+ 0) /* Streaming SIMD Extensions-3 */
@@ -113,5 +114,6 @@ 
#define cpu_has_centaur_mcr    0

#define cpu_has_centaur_mcr    0

#define cpu_has_clflush	       boot_cpu_has(X86_FEATURE_CLFLSH)

#define cpu_has_clflush	       boot_cpu_has(X86_FEATURE_CLFLSH)

#define cpu_has_ds 	       boot_cpu_has(X86_FEATURE_DS)

#define cpu_has_ds 	       boot_cpu_has(X86_FEATURE_DS)

#define cpu_has_pebs 	       boot_cpu_has(X86_FEATURE_PEBS)





#endif /* __ASM_X8664_CPUFEATURE_H */
 
#endif /* __ASM_X8664_CPUFEATURE_H */