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Commit 35cb6f3b authored Feb 10, 2015 by Damien Lespiau Committed by Daniel Vetter Feb 13, 2015

drm/i915/bdw: Implement WaForceContextSaveRestoreNonCoherent



v2: Reorder defines (Ben)
v3: More bikesheds, this time re-ordering comments! (Chris)

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
[danvet: Resolve conflict.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

parent c57e3551

drivers/gpu/drm/i915/i915_reg.h

+3 −2

Original line number	Diff line number	Diff line
		@@ -5260,9 +5260,10 @@ enum skl_disp_power_wells {

		/* GEN8 chicken */
		#define HDC_CHICKEN0 0x7300
		#define HDC_FORCE_NON_COHERENT (1<<4)
		#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
		#define HDC_FENCE_DEST_SLM_DISABLE (1<<14)
		#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
		#define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1<<5)
		#define HDC_FORCE_NON_COHERENT (1<<4)

		/* WaCatErrorRejectionIssue */
		#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030

drivers/gpu/drm/i915/intel_ringbuffer.c

+5 −3

Original line number	Diff line number	Diff line
		@@ -788,12 +788,14 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
		* workaround for for a possible hang in the unlikely event a TLB
		* invalidation occurs during a PSD flush.
		*/
		/* WaForceEnableNonCoherent:bdw */
		/* WaHdcDisableFetchWhenMasked:bdw */
		/* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */
		WA_SET_BIT_MASKED(HDC_CHICKEN0,
		/* WaForceEnableNonCoherent:bdw */
		HDC_FORCE_NON_COHERENT \|
		/* WaForceContextSaveRestoreNonCoherent:bdw */
		HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT \|
		/* WaHdcDisableFetchWhenMasked:bdw */
		HDC_DONOT_FETCH_MEM_WHEN_MASKED \|
		/* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
		(IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));

		/* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: