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Commit 35b21d39 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nvd0/disp: call into core to handle dac power state changes 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 74b66850

drivers/gpu/drm/nouveau/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -137,6 +137,7 @@ nouveau-y += core/engine/disp/nva0.o 
nouveau-y += core/engine/disp/nva3.o

nouveau-y += core/engine/disp/nvd0.o

nouveau-y += core/engine/disp/nve0.o

nouveau-y += core/engine/disp/dacnv50.o

nouveau-y += core/engine/disp/sornv50.o

nouveau-y += core/engine/disp/sornvd0.o

nouveau-y += core/engine/disp/vga.o

drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c

0 → 100644
+88 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2012 Red Hat Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: Ben Skeggs

 */



#include <core/os.h>

#include <core/class.h>



#include <subdev/bios.h>

#include <subdev/bios/dcb.h>

#include <subdev/timer.h>



#include "nv50.h"



int

nv50_dac_power(struct nv50_disp_priv *priv, int or, u32 data)

{

	const u32 stat = (data & NV50_DISP_DAC_PWR_HSYNC) |

		         (data & NV50_DISP_DAC_PWR_VSYNC) |

		         (data & NV50_DISP_DAC_PWR_DATA) |

		         (data & NV50_DISP_DAC_PWR_STATE);

	const u32 doff = (or * 0x800);

	nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000);

	nv_mask(priv, 0x61a004 + doff, 0xc000007f, 0x80000000 | stat);

	nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000);

	return 0;

}



int

nv50_dac_sense(struct nv50_disp_priv *priv, int or)

{

	const u32 doff = (or * 0x800);

	int load = -EINVAL;

	nv_wr32(priv, 0x61a00c + doff, 0x00100000);

	udelay(9500);

	nv_wr32(priv, 0x61a00c + doff, 0x80000000);

	load = (nv_rd32(priv, 0x61a00c + doff) & 0x38000000) >> 27;

	nv_wr32(priv, 0x61a00c + doff, 0x00000000);

	return load;

}



int

nv50_dac_mthd(struct nouveau_object *object, u32 mthd, void *args, u32 size)

{

	struct nv50_disp_priv *priv = (void *)object->engine;

	const u8 or = (mthd & NV50_DISP_DAC_MTHD_OR);

	u32 *data = args;

	int ret;



	if (size < sizeof(u32))

		return -EINVAL;



	switch (mthd & ~0x3f) {

	case NV50_DISP_DAC_PWR:

		ret = priv->dac.power(priv, or, data[0]);

		break;

	case NV50_DISP_DAC_LOAD:

		ret = priv->dac.sense(priv, or);

		if (ret >= 0) {

			data[0] = ret;

			ret = 0;

		}

		break;

	default:

		BUG_ON(1);

	}



	return ret;

}

drivers/gpu/drm/nouveau/core/engine/disp/nv50.h

+8 −0
Original line number Diff line number Diff line
@@ -18,6 +18,8 @@ struct nv50_disp_priv { 
	} head;

	struct {

		int nr;

		int (*power)(struct nv50_disp_priv *, int dac, u32 data);

		int (*sense)(struct nv50_disp_priv *, int dac);

	} dac;

	struct {

		int nr;
@@ -36,6 +38,12 @@ struct nv50_disp_priv { 


extern struct nouveau_omthds nva3_disp_base_omthds[];



#define DAC_MTHD(n) (n), (n) + 0x03



int nv50_dac_mthd(struct nouveau_object *, u32, void *, u32);

int nv50_dac_power(struct nv50_disp_priv *, int, u32);

int nv50_dac_sense(struct nv50_disp_priv *, int);



#define SOR_MTHD(n) (n), (n) + 0x3f



int nv50_sor_mthd(struct nouveau_object *, u32, void *, u32);

drivers/gpu/drm/nouveau/core/engine/disp/nva3.c

+2 −0
Original line number Diff line number Diff line
@@ -48,6 +48,8 @@ nva3_disp_base_omthds[] = { 
	{ SOR_MTHD(NV94_DISP_SOR_DP_DRVCTL(1)), nv50_sor_mthd },

	{ SOR_MTHD(NV94_DISP_SOR_DP_DRVCTL(2)), nv50_sor_mthd },

	{ SOR_MTHD(NV94_DISP_SOR_DP_DRVCTL(3)), nv50_sor_mthd },

	{ DAC_MTHD(NV50_DISP_DAC_PWR)         , nv50_dac_mthd },

	{ DAC_MTHD(NV50_DISP_DAC_LOAD)        , nv50_dac_mthd },

	{},

};

drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c

+2 −0
Original line number Diff line number Diff line
@@ -896,6 +896,8 @@ nvd0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 
	priv->head.nr = nv_rd32(priv, 0x022448);

	priv->dac.nr = 3;

	priv->sor.nr = 4;

	priv->dac.power = nv50_dac_power;

	priv->dac.sense = nv50_dac_sense;

	priv->sor.power = nv50_sor_power;

	priv->sor.dp_train = nvd0_sor_dp_train;

	priv->sor.dp_lnkctl = nvd0_sor_dp_lnkctl;