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Commit 35131fdf authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: msm: Update SDM855 QMP PHY parameters for USB 3.1 Gen1" into msm-4.14

parents aa6343cc 0fc0570c

arch/arm64/boot/dts/qcom/sdm855-usb.dtsi

+19 −14
Original line number Diff line number Diff line
@@ -152,6 +152,7 @@ 
		     USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xde 0

		     USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0

		     USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0a 0

		     USB3_DP_QSERDES_COM_CMN_IPTRIM 0x14 0

		     USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x06 0

		     USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x06 0

		     USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0
@@ -184,6 +185,8 @@ 
		     USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xca 0

		     USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1e 0

		     USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0

		     USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0xd4 0

		     USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0xd0 0

		     USB3_DP_QSERDES_TXA_LANE_MODE_1 0x05 0

		     USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0

		     USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x04 0
@@ -196,7 +199,7 @@ 
		     USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08 0

		     USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x05 0

		     USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x05 0

		     USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x03 0

		     USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0f 0

		     USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0f 0

		     USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4a 0

		     USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x08 0
@@ -211,13 +214,15 @@ 
		     USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0xb6 0

		     USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x17 0

		     USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0x7c 0

		     USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0xd4 0

		     USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x54 0

		     USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0xdb 0

		     USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x39 0

		     USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0x31 0

		     USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0xfc 0

		     USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0xfc 0

		     USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0xff 0

		     USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x23 0

		     USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0x34 0

		     USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04 0

		     USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x30 0

		     USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0xd4 0

		     USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0xd0 0

		     USB3_DP_QSERDES_TXB_LANE_MODE_1 0x05 0

		     USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0

		     USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x04 0
@@ -230,7 +235,7 @@ 
		     USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08 0

		     USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x05 0

		     USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x05 0

		     USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x03 0

		     USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0f 0

		     USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0f 0

		     USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4a 0

		     USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x08 0
@@ -245,21 +250,21 @@ 
		     USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0xb6 0

		     USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x17 0

		     USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0x7c 0

		     USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0xd4 0

		     USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x54 0

		     USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0xdb 0

		     USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x39 0

		     USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0x31 0

		     USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0xfc 0

		     USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0xfc 0

		     USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0xff 0

		     USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x23 0

		     USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0x34 0

		     USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04 0

		     USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x30 0

		     USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xd0 0

		     USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x17 0

		     USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20 0

		     USB3_DP_PCS_RX_SIGDET_LVL 0x88 0

		     USB3_DP_PCS_RX_SIGDET_LVL 0xaa 0

		     USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88 0

		     USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13 0

		     USB3_DP_PCS_EQ_CONFIG1 0x0d 0

		     USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x64 0

		     USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xf8 0

		     USB3_DP_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x55 0

		     USB3_DP_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x30 0

		     USB3_DP_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x05 0