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Commit 34e8be59 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "regulator: spm-regulator: Add support for HFS430 type regulators"

parents c3905f3e aa579d97

drivers/regulator/spm-regulator.c

+69 −38
Original line number Diff line number Diff line 
/* Copyright (c) 2013-2017, The Linux Foundation. All rights reserved.

/* Copyright (c) 2013-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -52,6 +52,7 @@ enum qpnp_regulator_uniq_type { 
	QPNP_TYPE_FTS2p5,

	QPNP_TYPE_FTS426,

	QPNP_TYPE_ULT_HF,

	QPNP_TYPE_HFS430,

};



enum qpnp_regulator_type {
@@ -68,6 +69,7 @@ enum qpnp_regulator_subtype { 
	QPNP_FTS2p5_SUBTYPE	= 0x09,

	QPNP_FTS426_SUBTYPE	= 0x0A,

	QPNP_ULT_HF_SUBTYPE	= 0x0D,

	QPNP_HFS430_SUBTYPE	= 0x0A,

};



enum qpnp_logical_mode {
@@ -82,6 +84,7 @@ static const struct voltage_range fts2p5_range0 
static const struct voltage_range fts2p5_range1

					 = {160000, 700000, 2200000, 10000};

static const struct voltage_range fts426_range = {0, 320000, 1352000, 4000};

static const struct voltage_range hfs430_range = {0, 320000, 2040000, 8000};

static const struct voltage_range ult_hf_range0 = {375000, 375000, 1562500,

								12500};

static const struct voltage_range ult_hf_range1 = {750000, 750000, 1525000,
@@ -98,11 +101,11 @@ static const struct voltage_range hf_range1 = {1550000, 1550000, 3125000, 
#define QPNP_SMPS_REG_STEP_CTRL		0x61

#define QPNP_SMPS_REG_UL_LL_CTRL	0x68



/* FTS426 voltage control registers */

#define QPNP_FTS426_REG_VOLTAGE_LB		0x40

#define QPNP_FTS426_REG_VOLTAGE_UB		0x41

#define QPNP_FTS426_REG_VOLTAGE_VALID_LB	0x42

#define QPNP_FTS426_REG_VOLTAGE_VALID_UB	0x43

/* FTS426/HFS430 voltage control registers */

#define QPNP_FTS426_HFS430_REG_VOLTAGE_LB	0x40

#define QPNP_FTS426_HFS430_REG_VOLTAGE_UB	0x41

#define QPNP_FTS426_HFS430_REG_VOLTAGE_VALID_LB	0x42

#define QPNP_FTS426_HFS430_REG_VOLTAGE_VALID_UB	0x43



/* HF voltage limit registers */

#define QPNP_HF_REG_VOLTAGE_ULS		0x69
@@ -112,9 +115,9 @@ static const struct voltage_range hf_range1 = {1550000, 1550000, 3125000, 
#define QPNP_FTS_REG_VOLTAGE_ULS_VALID	0x6A

#define QPNP_FTS_REG_VOLTAGE_LLS_VALID	0x6C



/* FTS426 voltage limit registers */

#define QPNP_FTS426_REG_VOLTAGE_ULS_LB	0x68

#define QPNP_FTS426_REG_VOLTAGE_ULS_UB	0x69

/* FTS426/HFS430 voltage limit registers */

#define QPNP_FTS426_HFS430_REG_VOLTAGE_ULS_LB	0x68

#define QPNP_FTS426_HFS430_REG_VOLTAGE_ULS_UB	0x69



/* Common regulator UL & LL limits control register layout */

#define QPNP_COMMON_UL_EN_MASK		0x80
@@ -122,19 +125,20 @@ static const struct voltage_range hf_range1 = {1550000, 1550000, 3125000, 


#define QPNP_SMPS_MODE_PWM		0x80

#define QPNP_SMPS_MODE_AUTO		0x40

#define QPNP_FTS426_MODE_PWM		0x07

#define QPNP_FTS426_MODE_AUTO		0x06

#define QPNP_FTS426_HFS430_MODE_PWM	0x07

#define QPNP_FTS426_HFS430_MODE_AUTO	0x06



#define QPNP_SMPS_STEP_CTRL_STEP_MASK	0x18

#define QPNP_SMPS_STEP_CTRL_STEP_SHIFT	3

#define QPNP_SMPS_STEP_CTRL_DELAY_MASK	0x07

#define QPNP_SMPS_STEP_CTRL_DELAY_SHIFT	0

#define QPNP_FTS426_STEP_CTRL_DELAY_MASK	0x03

#define QPNP_FTS426_STEP_CTRL_DELAY_SHIFT	0

#define QPNP_FTS426_HFS430_STEP_CTRL_DELAY_MASK		0x03

#define QPNP_FTS426_HFS430_STEP_CTRL_DELAY_SHIFT	0



/* Clock rate in kHz of the FTS2 regulator reference clock. */

#define QPNP_SMPS_CLOCK_RATE		19200

#define QPNP_FTS426_CLOCK_RATE		4800

#define QPNP_HFS430_CLOCK_RATE		1600



/* Time to delay in us to ensure that a mode change has completed. */

#define QPNP_FTS2_MODE_CHANGE_DELAY	50
@@ -145,7 +149,7 @@ static const struct voltage_range hf_range1 = {1550000, 1550000, 3125000, 
/* Minimum voltage stepper delay for each step. */

#define QPNP_FTS2_STEP_DELAY		8

#define QPNP_HF_STEP_DELAY		20

#define QPNP_FTS426_STEP_DELAY		2

#define QPNP_FTS426_HFS430_STEP_DELAY	2



/* Arbitrarily large max step size used to avoid possible numerical overflow */

#define SPM_REGULATOR_MAX_STEP_UV	10000000
@@ -156,8 +160,8 @@ static const struct voltage_range hf_range1 = {1550000, 1550000, 3125000, 
 */

#define QPNP_FTS2_STEP_MARGIN_NUM	4

#define QPNP_FTS2_STEP_MARGIN_DEN	5

#define QPNP_FTS426_STEP_MARGIN_NUM	10

#define QPNP_FTS426_STEP_MARGIN_DEN	11

#define QPNP_FTS426_HFS430_STEP_MARGIN_NUM	10

#define QPNP_FTS426_HFS430_STEP_MARGIN_DEN	11



/*

 * Settling delay for FTS2.5
@@ -204,7 +208,8 @@ static int spm_regulator_uv_to_vlevel(struct spm_vreg *vreg, int uV) 
{

	int vlevel;



	if (vreg->regulator_type == QPNP_TYPE_FTS426)

	if (vreg->regulator_type == QPNP_TYPE_FTS426

		|| vreg->regulator_type == QPNP_TYPE_HFS430)

		return roundup(uV, vreg->range->step_uV) / 1000;



	vlevel = DIV_ROUND_UP(uV - vreg->range->min_uV, vreg->range->step_uV);
@@ -221,7 +226,8 @@ static int spm_regulator_uv_to_vlevel(struct spm_vreg *vreg, int uV) 


static int spm_regulator_vlevel_to_uv(struct spm_vreg *vreg, int vlevel)

{

	if (vreg->regulator_type == QPNP_TYPE_FTS426)

	if (vreg->regulator_type == QPNP_TYPE_FTS426

		|| vreg->regulator_type == QPNP_TYPE_HFS430)

		return vlevel * 1000;

	/*

	 * Calculate ULT HF buck VSET based on range:
@@ -243,6 +249,10 @@ static unsigned spm_regulator_vlevel_to_selector(struct spm_vreg *vreg, 
	    && vreg->range == &ult_hf_range1)

		vlevel &= ~ULT_SMPS_RANGE_SPLIT;



	if (vreg->regulator_type == QPNP_TYPE_HFS430)

		vlevel = spm_regulator_vlevel_to_uv(vreg, vlevel)

				/ vreg->range->step_uV;



	return vlevel - (vreg->range->set_point_min_uV - vreg->range->min_uV)

				/ vreg->range->step_uV;

}
@@ -252,9 +262,11 @@ static int qpnp_smps_read_voltage(struct spm_vreg *vreg) 
	int rc;

	u8 val[2] = {0};



	if (vreg->regulator_type == QPNP_TYPE_FTS426) {

	if (vreg->regulator_type == QPNP_TYPE_FTS426

		|| vreg->regulator_type == QPNP_TYPE_HFS430) {

		rc = regmap_bulk_read(vreg->regmap,

			vreg->spmi_base_addr + QPNP_FTS426_REG_VOLTAGE_VALID_LB,

				vreg->spmi_base_addr

				+ QPNP_FTS426_HFS430_REG_VOLTAGE_VALID_LB,

				val, 2);

		if (rc) {

			dev_err(&vreg->pdev->dev, "%s: could not read voltage setpoint registers, rc=%d\n",
@@ -289,9 +301,11 @@ static int qpnp_smps_write_voltage(struct spm_vreg *vreg, unsigned vlevel) 
	reg[0] = vlevel & 0xFF;

	reg[1] = (vlevel >> 8) & 0xFF;



	if (vreg->regulator_type == QPNP_TYPE_FTS426) {

	if (vreg->regulator_type == QPNP_TYPE_FTS426

		|| vreg->regulator_type == QPNP_TYPE_HFS430) {

		rc = regmap_bulk_write(vreg->regmap,

			  vreg->spmi_base_addr + QPNP_FTS426_REG_VOLTAGE_LB,

			  vreg->spmi_base_addr

			  + QPNP_FTS426_HFS430_REG_VOLTAGE_LB,

			  reg, 2);

	} else {

		rc = regmap_write(vreg->regmap,
@@ -309,8 +323,9 @@ static int qpnp_smps_write_voltage(struct spm_vreg *vreg, unsigned vlevel) 
static inline enum qpnp_logical_mode qpnp_regval_to_mode(struct spm_vreg *vreg,

							u8 regval)

{

	if (vreg->regulator_type == QPNP_TYPE_FTS426)

		return (regval == QPNP_FTS426_MODE_PWM)

	if (vreg->regulator_type == QPNP_TYPE_FTS426

		|| vreg->regulator_type == QPNP_TYPE_HFS430)

		return (regval == QPNP_FTS426_HFS430_MODE_PWM)

			? QPNP_LOGICAL_MODE_PWM : QPNP_LOGICAL_MODE_AUTO;

	else

		return (regval & QPNP_SMPS_MODE_PWM)
@@ -320,9 +335,11 @@ static inline enum qpnp_logical_mode qpnp_regval_to_mode(struct spm_vreg *vreg, 
static inline u8 qpnp_mode_to_regval(struct spm_vreg *vreg,

					enum qpnp_logical_mode mode)

{

	if (vreg->regulator_type == QPNP_TYPE_FTS426)

	if (vreg->regulator_type == QPNP_TYPE_FTS426

		|| vreg->regulator_type == QPNP_TYPE_HFS430)

		return (mode == QPNP_LOGICAL_MODE_PWM)

			? QPNP_FTS426_MODE_PWM : QPNP_FTS426_MODE_AUTO;

			? QPNP_FTS426_HFS430_MODE_PWM

			: QPNP_FTS426_HFS430_MODE_AUTO;

	else

		return (mode == QPNP_LOGICAL_MODE_PWM)

			? QPNP_SMPS_MODE_PWM : QPNP_SMPS_MODE_AUTO;
@@ -748,6 +765,9 @@ static int qpnp_smps_check_type(struct spm_vreg *vreg) 
	} else if (type[0] == QPNP_FTS426_TYPE

					&& type[1] == QPNP_FTS426_SUBTYPE) {

		vreg->regulator_type = QPNP_TYPE_FTS426;

	} else if (type[0] == QPNP_HF_TYPE

					&& type[1] == QPNP_HFS430_SUBTYPE) {

		vreg->regulator_type = QPNP_TYPE_HFS430;

	} else if (type[0] == QPNP_ULT_HF_TYPE

					&& type[1] == QPNP_ULT_HF_SUBTYPE) {

		vreg->regulator_type = QPNP_TYPE_ULT_HF;
@@ -901,16 +921,20 @@ static int qpnp_smps_init_step_rate(struct spm_vreg *vreg) 


	/* ULT and FTS426 bucks do not support steps */

	if (vreg->regulator_type != QPNP_TYPE_ULT_HF && vreg->regulator_type !=

			QPNP_TYPE_FTS426)

		QPNP_TYPE_FTS426  && vreg->regulator_type != QPNP_TYPE_HFS430)

		step = (reg & QPNP_SMPS_STEP_CTRL_STEP_MASK)

			>> QPNP_SMPS_STEP_CTRL_STEP_SHIFT;



	if (vreg->regulator_type == QPNP_TYPE_FTS426) {

		delay = (reg & QPNP_FTS426_STEP_CTRL_DELAY_MASK)

			>> QPNP_FTS426_STEP_CTRL_DELAY_SHIFT;

	if (vreg->regulator_type == QPNP_TYPE_FTS426

		|| vreg->regulator_type == QPNP_TYPE_HFS430) {

		delay = (reg & QPNP_FTS426_HFS430_STEP_CTRL_DELAY_MASK)

			>> QPNP_FTS426_HFS430_STEP_CTRL_DELAY_SHIFT;



		/* step_rate has units of uV/us. */

		vreg->step_rate = QPNP_FTS426_CLOCK_RATE * vreg->range->step_uV;

		vreg->step_rate = ((vreg->regulator_type == QPNP_TYPE_FTS426)

					? QPNP_FTS426_CLOCK_RATE

					: QPNP_HFS430_CLOCK_RATE)

					* vreg->range->step_uV;

	} else {

		delay = (reg & QPNP_SMPS_STEP_CTRL_DELAY_MASK)

			>> QPNP_SMPS_STEP_CTRL_DELAY_SHIFT;
@@ -923,14 +947,18 @@ static int qpnp_smps_init_step_rate(struct spm_vreg *vreg) 
	if ((vreg->regulator_type == QPNP_TYPE_ULT_HF)

			|| (vreg->regulator_type == QPNP_TYPE_HF))

		vreg->step_rate /= 1000 * (QPNP_HF_STEP_DELAY << delay);

	else if (vreg->regulator_type == QPNP_TYPE_FTS426)

		vreg->step_rate /= 1000 * (QPNP_FTS426_STEP_DELAY << delay);

	else if (vreg->regulator_type == QPNP_TYPE_FTS426

			|| vreg->regulator_type == QPNP_TYPE_HFS430)

		vreg->step_rate /= 1000 * (QPNP_FTS426_HFS430_STEP_DELAY

						<< delay);

	else

		vreg->step_rate /= 1000 * (QPNP_FTS2_STEP_DELAY << delay);



	if (vreg->regulator_type == QPNP_TYPE_FTS426)

		vreg->step_rate = vreg->step_rate * QPNP_FTS426_STEP_MARGIN_NUM

					/ QPNP_FTS426_STEP_MARGIN_DEN;

	if (vreg->regulator_type == QPNP_TYPE_FTS426

			|| vreg->regulator_type == QPNP_TYPE_HFS430)

		vreg->step_rate = vreg->step_rate

					* QPNP_FTS426_HFS430_STEP_MARGIN_NUM

					/ QPNP_FTS426_HFS430_STEP_MARGIN_DEN;

	else

		vreg->step_rate = vreg->step_rate * QPNP_FTS2_STEP_MARGIN_NUM

					/ QPNP_FTS2_STEP_MARGIN_DEN;
@@ -994,8 +1022,9 @@ static int qpnp_smps_check_constraints(struct spm_vreg *vreg, 


		break;

	case QPNP_TYPE_FTS426:

	case QPNP_TYPE_HFS430:

		rc = regmap_bulk_read(vreg->regmap, vreg->spmi_base_addr

					+ QPNP_FTS426_REG_VOLTAGE_ULS_LB,

					+ QPNP_FTS426_HFS430_REG_VOLTAGE_ULS_LB,

					reg, 2);

		if (rc) {

			dev_err(&vreg->pdev->dev, "%s: could not read voltage limit registers, rc=%d\n",
@@ -1167,6 +1196,8 @@ static int spm_regulator_probe(struct platform_device *pdev) 
		rc = qpnp_smps_init_range(vreg, &fts2p5_range0, &fts2p5_range1);

	else if (vreg->regulator_type == QPNP_TYPE_FTS426)

		vreg->range = &fts426_range;

	else if (vreg->regulator_type == QPNP_TYPE_HFS430)

		vreg->range = &hfs430_range;

	else if (vreg->regulator_type == QPNP_TYPE_HF)

		rc = qpnp_smps_init_range(vreg, &hf_range0, &hf_range1);

	else if (vreg->regulator_type == QPNP_TYPE_ULT_HF)