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Commit 34d9b689 authored by Sujith Manoharan's avatar Sujith Manoharan Committed by John W. Linville
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ath9k: Fix Carrier Leak calibration for SoC chips 



CL calibration is applicable for all chips and the
enable/disable knob comes via the INI file. For PCOEM
chips, the calibration data is reused when Fast Channel Change
is used. Caldata reuse is not enabled for SoC chips, so remove
the CL post processing code.

Signed-off-by: default avatarSujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent c20a2c59

drivers/net/wireless/ath/ath9k/ar9003_calib.c

+2 −25
Original line number Diff line number Diff line
@@ -1236,21 +1236,14 @@ static bool ar9003_hw_init_cal_soc(struct ath_hw *ah, 
	bool txiqcal_done = false;

	bool is_reusable = true, status = true;

	bool run_agc_cal = false, sep_iq_cal = false;

	u32 rx_delay = 0;



	/* Use chip chainmask only for calibration */

	ar9003_hw_set_chain_masks(ah, ah->caps.rx_chainmask, ah->caps.tx_chainmask);



	if (ah->enabled_cals & TX_CL_CAL) {

		if (caldata && test_bit(TXCLCAL_DONE, &caldata->cal_flags))

			REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL,

				    AR_PHY_CL_CAL_ENABLE);

		else {

			REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL,

				    AR_PHY_CL_CAL_ENABLE);

		REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);

		run_agc_cal = true;

	}

	}



	if (IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan))

		goto skip_tx_iqcal;
@@ -1285,15 +1278,6 @@ static bool ar9003_hw_init_cal_soc(struct ath_hw *ah, 
		REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);

	}



	if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) {

		rx_delay = REG_READ(ah, AR_PHY_RX_DELAY);

		/* Disable BB_active */

		REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);

		udelay(5);

		REG_WRITE(ah, AR_PHY_RX_DELAY, AR_PHY_RX_DELAY_DELAY);

		REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);

	}



	if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) {

		/* Calibrate the AGC */

		REG_WRITE(ah, AR_PHY_AGC_CONTROL,
@@ -1306,11 +1290,6 @@ static bool ar9003_hw_init_cal_soc(struct ath_hw *ah, 
				       0, AH_WAIT_TIMEOUT);

	}



	if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) {

		REG_WRITE(ah, AR_PHY_RX_DELAY, rx_delay);

		udelay(5);

	}



	if (!status) {

		ath_dbg(common, CALIBRATE,

			"offset calibration failed to complete in %d ms; noisy environment?\n",
@@ -1323,8 +1302,6 @@ static bool ar9003_hw_init_cal_soc(struct ath_hw *ah, 
	else if (caldata && test_bit(TXIQCAL_DONE, &caldata->cal_flags))

		ar9003_hw_tx_iq_cal_reload(ah);



	ar9003_hw_cl_cal_post_proc(ah, is_reusable);



	/* Revert chainmask to runtime parameters */

	ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);

drivers/net/wireless/ath/ath9k/ar9003_phy.c

+5 −4
Original line number Diff line number Diff line
@@ -641,12 +641,13 @@ static void ar9003_hw_override_ini(struct ath_hw *ah) 
		else

			ah->enabled_cals &= ~TX_IQ_CAL;



	}



	if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)

		ah->enabled_cals |= TX_CL_CAL;

	else

		ah->enabled_cals &= ~TX_CL_CAL;

}

}



static void ar9003_hw_prog_ini(struct ath_hw *ah,

			       struct ar5416IniArray *iniArr,