Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 34cba900 authored by Javier Martinez Canillas's avatar Javier Martinez Canillas Committed by Sylwester Nawrocki
Browse files

clk: samsung: exynos5420: Set ID for aclk333 gate clock 



The aclk333 clock needs to be ungated during the MFC power domain switch,
so set the clock ID to allow the Exynos power domain logic to lookup this
clock if is defined in the MFC PD device tree node.

Signed-off-by: default avatarJavier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: default avatarKrzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: default avatarMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
parent 41743a19

drivers/clk/samsung/clk-exynos5420.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -946,7 +946,7 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { 
			GATE_BUS_TOP, 13, 0, 0),

			GATE_BUS_TOP, 13, 0, 0),

	GATE(0, "aclk166", "mout_user_aclk166",

	GATE(0, "aclk166", "mout_user_aclk166",

			GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),

			GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),

	GATE(0, "aclk333", "mout_user_aclk333",

	GATE(CLK_ACLK333, "aclk333", "mout_user_aclk333",

			GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0),

			GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0),

	GATE(0, "aclk400_isp", "mout_user_aclk400_isp",

	GATE(0, "aclk400_isp", "mout_user_aclk400_isp",

			GATE_BUS_TOP, 16, 0, 0),

			GATE_BUS_TOP, 16, 0, 0),