Loading drivers/gpu/msm/adreno_a6xx.c +0 −9 Original line number Diff line number Diff line Loading @@ -1798,14 +1798,6 @@ static struct adreno_irq a6xx_irq = { .mask = A6XX_INT_MASK, }; static struct adreno_snapshot_sizes a6xx_snap_sizes = { .cp_pfp = 0x33, }; static struct adreno_snapshot_data a6xx_snapshot_data = { .sect_sizes = &a6xx_snap_sizes, }; static struct adreno_coresight_register a6xx_coresight_regs[] = { { A6XX_DBGC_CFG_DBGBUS_SEL_A }, { A6XX_DBGC_CFG_DBGBUS_SEL_B }, Loading Loading @@ -2988,7 +2980,6 @@ struct adreno_gpudev adreno_a6xx_gpudev = { .start = a6xx_start, .snapshot = a6xx_snapshot, .irq = &a6xx_irq, .snapshot_data = &a6xx_snapshot_data, .irq_trace = trace_kgsl_a5xx_irq_status, .num_prio_levels = KGSL_PRIORITY_MAX_RB_LEVELS, .platform_setup = a6xx_platform_setup, Loading drivers/gpu/msm/adreno_a6xx_snapshot.c +1 −3 Original line number Diff line number Diff line Loading @@ -1493,7 +1493,6 @@ void a6xx_snapshot(struct adreno_device *adreno_dev, struct kgsl_device *device = KGSL_DEVICE(adreno_dev); struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev); struct gmu_dev_ops *gmu_dev_ops = GMU_DEVICE_OPS(device); struct adreno_snapshot_data *snap_data = gpudev->snapshot_data; bool sptprac_on, gx_on = true; unsigned int i, roq_size; Loading Loading @@ -1544,8 +1543,7 @@ void a6xx_snapshot(struct adreno_device *adreno_dev, /* CP_SQE indexed registers */ kgsl_snapshot_indexed_registers(device, snapshot, A6XX_CP_SQE_STAT_ADDR, A6XX_CP_SQE_STAT_DATA, 0, snap_data->sect_sizes->cp_pfp); A6XX_CP_SQE_STAT_ADDR, A6XX_CP_SQE_STAT_DATA, 0, 0x33); /* CP_DRAW_STATE */ kgsl_snapshot_indexed_registers(device, snapshot, Loading Loading
drivers/gpu/msm/adreno_a6xx.c +0 −9 Original line number Diff line number Diff line Loading @@ -1798,14 +1798,6 @@ static struct adreno_irq a6xx_irq = { .mask = A6XX_INT_MASK, }; static struct adreno_snapshot_sizes a6xx_snap_sizes = { .cp_pfp = 0x33, }; static struct adreno_snapshot_data a6xx_snapshot_data = { .sect_sizes = &a6xx_snap_sizes, }; static struct adreno_coresight_register a6xx_coresight_regs[] = { { A6XX_DBGC_CFG_DBGBUS_SEL_A }, { A6XX_DBGC_CFG_DBGBUS_SEL_B }, Loading Loading @@ -2988,7 +2980,6 @@ struct adreno_gpudev adreno_a6xx_gpudev = { .start = a6xx_start, .snapshot = a6xx_snapshot, .irq = &a6xx_irq, .snapshot_data = &a6xx_snapshot_data, .irq_trace = trace_kgsl_a5xx_irq_status, .num_prio_levels = KGSL_PRIORITY_MAX_RB_LEVELS, .platform_setup = a6xx_platform_setup, Loading
drivers/gpu/msm/adreno_a6xx_snapshot.c +1 −3 Original line number Diff line number Diff line Loading @@ -1493,7 +1493,6 @@ void a6xx_snapshot(struct adreno_device *adreno_dev, struct kgsl_device *device = KGSL_DEVICE(adreno_dev); struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev); struct gmu_dev_ops *gmu_dev_ops = GMU_DEVICE_OPS(device); struct adreno_snapshot_data *snap_data = gpudev->snapshot_data; bool sptprac_on, gx_on = true; unsigned int i, roq_size; Loading Loading @@ -1544,8 +1543,7 @@ void a6xx_snapshot(struct adreno_device *adreno_dev, /* CP_SQE indexed registers */ kgsl_snapshot_indexed_registers(device, snapshot, A6XX_CP_SQE_STAT_ADDR, A6XX_CP_SQE_STAT_DATA, 0, snap_data->sect_sizes->cp_pfp); A6XX_CP_SQE_STAT_ADDR, A6XX_CP_SQE_STAT_DATA, 0, 0x33); /* CP_DRAW_STATE */ kgsl_snapshot_indexed_registers(device, snapshot, Loading