Merge "msm: kgsl: Use DOMAIN_ATTR_USE_LLC_NWA attribute" (346cd0b0) · Commits · e / devices / android_kernel_oneplus_sm8150

drivers/gpu/msm/a6xx_reg.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -814,6 +814,7 @@
		#define GBIF_AXI1_WRITE_DATA_TOTAL_BEATS 47

		/* GBIF registers */
		#define A6XX_GBIF_SCACHE_CNTL1 0x3c02
		#define A6XX_GBIF_QSB_SIDE0 0x3c03
		#define A6XX_GBIF_QSB_SIDE1 0x3c04
		#define A6XX_GBIF_QSB_SIDE2 0x3c05

drivers/gpu/msm/adreno.c

+28 −2

Original line number	Diff line number	Diff line
		@@ -112,8 +112,8 @@ static struct adreno_device device_3d0 = {
		.profile.enabled = false,
		.active_list = LIST_HEAD_INIT(device_3d0.active_list),
		.active_list_lock = __SPIN_LOCK_UNLOCKED(device_3d0.active_list_lock),
		.gpu_llc_slice_enable = false,
		.gpuhtw_llc_slice_enable = false,
		.gpu_llc_slice_enable = true,
		.gpuhtw_llc_slice_enable = true,
		.preempt = {
		.preempt_level = 1,
		.skipsaverestore = 1,
		@@ -1330,6 +1330,24 @@ static int adreno_probe(struct platform_device *pdev)
		/* Initialize coresight for the target */
		adreno_coresight_init(adreno_dev);

		/* Get the system cache slice descriptor for GPU */
		adreno_dev->gpu_llc_slice = adreno_llc_getd(&pdev->dev, "gpu");
		if (IS_ERR(adreno_dev->gpu_llc_slice)) {
		KGSL_DRV_WARN(device,
		"Failed to get GPU LLC slice descriptor %ld\n",
		PTR_ERR(adreno_dev->gpu_llc_slice));
		adreno_dev->gpu_llc_slice = NULL;
		}

		/* Get the system cache slice descriptor for GPU pagetables */
		adreno_dev->gpuhtw_llc_slice = adreno_llc_getd(&pdev->dev, "gpuhtw");
		if (IS_ERR(adreno_dev->gpuhtw_llc_slice)) {
		KGSL_DRV_WARN(device,
		"Failed to get gpuhtw LLC slice descriptor %ld\n",
		PTR_ERR(adreno_dev->gpuhtw_llc_slice));
		adreno_dev->gpuhtw_llc_slice = NULL;
		}

		#ifdef CONFIG_INPUT
		if (!device->pwrctrl.input_disable) {
		adreno_input_handler.private = device;
		@@ -1959,6 +1977,14 @@ static int _adreno_start(struct adreno_device *adreno_dev)
		/* Start the GPU */
		gpudev->start(adreno_dev);

		/*
		* The system cache control registers
		* live on the CX/GX rail. Hence need
		* reprogramming everytime the GPU
		* comes out of power collapse.
		*/
		adreno_llc_setup(device);

		/* Re-initialize the coresight registers if applicable */
		adreno_coresight_start(adreno_dev);

drivers/gpu/msm/adreno_a6xx.c

+25 −4

Original line number	Diff line number	Diff line
		@@ -1440,18 +1440,25 @@ static void a6xx_llc_configure_gpu_scid(struct adreno_device *adreno_dev)
		uint32_t gpu_scid;
		uint32_t gpu_cntl1_val = 0;
		int i;
		void __iomem *gpu_cx_reg;

		gpu_scid = adreno_llc_get_scid(adreno_dev->gpu_llc_slice);
		for (i = 0; i < A6XX_LLC_NUM_GPU_SCIDS; i++)
		gpu_cntl1_val = (gpu_cntl1_val << A6XX_GPU_LLC_SCID_NUM_BITS)
		\| gpu_scid;

		gpu_cx_reg = ioremap(A6XX_GPU_CX_REG_BASE, A6XX_GPU_CX_REG_SIZE);
		if (adreno_is_a640(adreno_dev)) {
		kgsl_regrmw(KGSL_DEVICE(adreno_dev), A6XX_GBIF_SCACHE_CNTL1,
		A6XX_GPU_LLC_SCID_MASK, gpu_cntl1_val);
		} else {
		void __iomem *gpu_cx_reg;

		gpu_cx_reg = ioremap(A6XX_GPU_CX_REG_BASE,
		A6XX_GPU_CX_REG_SIZE);
		_reg_rmw(gpu_cx_reg + A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_1,
		A6XX_GPU_LLC_SCID_MASK, gpu_cntl1_val);
		iounmap(gpu_cx_reg);
		}
		}

		/*
		* a6xx_llc_configure_gpuhtw_scid() - Program the SCID for GPU pagetables
		@@ -1462,6 +1469,13 @@ static void a6xx_llc_configure_gpuhtw_scid(struct adreno_device *adreno_dev)
		uint32_t gpuhtw_scid;
		void __iomem *gpu_cx_reg;

		/*
		* On A640, the GPUHTW SCID is configured via a NoC override in the
		* XBL image.
		*/
		if (adreno_is_a640(adreno_dev))
		return;

		gpuhtw_scid = adreno_llc_get_scid(adreno_dev->gpuhtw_llc_slice);

		gpu_cx_reg = ioremap(A6XX_GPU_CX_REG_BASE, A6XX_GPU_CX_REG_SIZE);
		@@ -1479,6 +1493,13 @@ static void a6xx_llc_enable_overrides(struct adreno_device *adreno_dev)
		{
		void __iomem *gpu_cx_reg;

		/*
		* Attributes override through GBIF is not supported with MMU-500.
		* Attributes are used as configured through SMMU pagetable entries.
		*/
		if (adreno_is_a640(adreno_dev))
		return;

		/*
		* 0x3: readnoallocoverrideen=0
		* read-no-alloc=0 - Allocate lines on read miss

drivers/gpu/msm/kgsl_iommu.c

+21 −5

Original line number	Diff line number	Diff line
		@@ -1164,8 +1164,13 @@ void _enable_gpuhtw_llc(struct kgsl_mmu mmu, struct kgsl_iommu_pt iommu_pt)
		return;

		/* Domain attribute to enable system cache for GPU pagetable walks */
		if (adreno_is_a640(adreno_dev))
		ret = iommu_domain_set_attr(iommu_pt->domain,
		DOMAIN_ATTR_USE_LLC_NWA, &gpuhtw_llc_enable);
		else
		ret = iommu_domain_set_attr(iommu_pt->domain,
		DOMAIN_ATTR_USE_UPSTREAM_HINT, &gpuhtw_llc_enable);

		/*
		* Warn that the system cache will not be used for GPU
		* pagetable walks. This is not a fatal error.
		@@ -1784,10 +1789,21 @@ static int _iommu_map_guard_page(struct kgsl_pagetable *pt,
		pad_size >> PAGE_SHIFT, protflags);
		}

		static unsigned int _get_protection_flags(struct kgsl_memdesc *memdesc)
		static unsigned int _get_protection_flags(struct kgsl_pagetable *pt,
		struct kgsl_memdesc *memdesc)
		{
		unsigned int flags = IOMMU_READ \| IOMMU_WRITE \|
		IOMMU_NOEXEC \| IOMMU_USE_UPSTREAM_HINT;
		IOMMU_NOEXEC;
		int ret, llc_nwa = 0;
		struct kgsl_iommu_pt *iommu_pt = pt->priv;

		ret = iommu_domain_get_attr(iommu_pt->domain,
		DOMAIN_ATTR_USE_LLC_NWA, &llc_nwa);

		if (ret \|\| (llc_nwa == 0))
		flags \|= IOMMU_USE_UPSTREAM_HINT;
		else
		flags \|= IOMMU_USE_LLC_NWA;

		if (memdesc->flags & KGSL_MEMFLAGS_GPUREADONLY)
		flags &= ~IOMMU_WRITE;
		@@ -1811,7 +1827,7 @@ kgsl_iommu_map(struct kgsl_pagetable *pt,
		int ret;
		uint64_t addr = memdesc->gpuaddr;
		uint64_t size = memdesc->size;
		unsigned int flags = _get_protection_flags(memdesc);
		unsigned int flags = _get_protection_flags(pt, memdesc);
		struct sg_table *sgt = NULL;

		/*
		@@ -1941,7 +1957,7 @@ static int kgsl_iommu_map_offset(struct kgsl_pagetable *pt,
		uint64_t size, uint64_t feature_flag)
		{
		int pg_sz;
		unsigned int protflags = _get_protection_flags(memdesc);
		unsigned int protflags = _get_protection_flags(pt, memdesc);
		int ret;
		struct sg_table *sgt = NULL;