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Commit 34251d4f authored by Can Guo's avatar Can Guo
Browse files

ARM: dts: msm: Add UFS support for SDM855 



Add UFS host controller and UFS PHY (attached to embedded UFS card)
for SDM855 platform.

Change-Id: I5f6facde6a65aef7b27c2e161ef8f008722bd360
Signed-off-by: default avatarCan Guo <cang@codeaurora.org>
parent d17f3b39

arch/arm64/boot/dts/qcom/sdm855-pinctrl.dtsi

+46 −0
Original line number Diff line number Diff line
@@ -19,5 +19,51 @@ 
		#gpio-cells = <2>;

		interrupt-controller;

		#interrupt-cells = <2>;



		ufs_dev_reset_assert: ufs_dev_reset_assert {

			config {

				pins = "ufs_reset";

				bias-pull-down;		/* default: pull down */

				/*

				 * UFS_RESET driver strengths are having

				 * different values/steps compared to typical

				 * GPIO drive strengths.

				 *

				 * Following table clarifies:

				 *

				 * HDRV value | UFS_RESET | Typical GPIO

				 *   (dec)    |   (mA)    |    (mA)

				 *     0      |   0.8     |    2

				 *     1      |   1.55    |    4

				 *     2      |   2.35    |    6

				 *     3      |   3.1     |    8

				 *     4      |   3.9     |    10

				 *     5      |   4.65    |    12

				 *     6      |   5.4     |    14

				 *     7      |   6.15    |    16

				 *

				 * POR value for UFS_RESET HDRV is 3 which means

				 * 3.1mA and we want to use that. Hence just

				 * specify 8mA to "drive-strength" binding and

				 * that should result into writing 3 to HDRV

				 * field.

				 */

				drive-strength = <8>;	/* default: 3.1 mA */

				output-low; /* active low reset */

			};

		};



		ufs_dev_reset_deassert: ufs_dev_reset_deassert {

			config {

				pins = "ufs_reset";

				bias-pull-down;		/* default: pull down */

				/*

				 * default: 3.1 mA

				 * check comments under ufs_dev_reset_assert

				 */

				drive-strength = <8>;

				output-high; /* active low reset */

			};

		};

	};

};

arch/arm64/boot/dts/qcom/sdm855.dtsi

+170 −0
Original line number Diff line number Diff line
@@ -26,6 +26,11 @@ 
	qcom,msm-id = <339 0x0>;

	interrupt-parent = <&intc>;



	aliases {

		ufshc1 = &ufshc_mem; /* Embedded UFS slot */

		ufshc2 = &ufshc_card; /* Removable UFS slot */

	};



	cpus {

		#address-cells = <2>;

		#size-cells = <0>;
@@ -511,6 +516,171 @@ 
			snps,hird-threshold = /bits/ 8 <0x10>;

		};

	};



	ufsphy_mem: ufsphy_mem@1d87000 {

		reg = <0x1d87000 0xda8>; /* PHY regs */

		reg-names = "phy_mem";

		#phy-cells = <0>;



		lanes-per-direction = <2>;



		status = "disabled";

	};



	ufshc_mem: ufshc@1d84000 {

		compatible = "qcom,ufshc";

		reg = <0x1d84000 0x2500>;

		interrupts = <0 265 0>;

		phys = <&ufsphy_mem>;

		phy-names = "ufsphy";



		lanes-per-direction = <2>;

		dev-ref-clk-freq = <0>; /* 19.2 MHz */



		clock-names =

			"tx_lane0_sync_clk",

			"rx_lane0_sync_clk",

			"rx_lane1_sync_clk";

		clocks =

			<&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,

			<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,

			<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;

		freq-table-hz =

			<0 0>,

			<0 0>,

			<0 0>;



		qcom,msm-bus,name = "ufshc_mem";

		qcom,msm-bus,num-cases = <22>;

		qcom,msm-bus,num-paths = <2>;

		qcom,msm-bus,vectors-KBps =

		/*

		 * During HS G3 UFS runs at nominal voltage corner, vote

		 * higher bandwidth to push other buses in the data path

		 * to run at nominal to achieve max throughput.

		 * 4GBps pushes BIMC to run at nominal.

		 * 200MBps pushes CNOC to run at nominal.

		 * Vote for half of this bandwidth for HS G3 1-lane.

		 * For max bandwidth, vote high enough to push the buses

		 * to run in turbo voltage corner.

		 */

		<123 512 0 0>, <1 757 0 0>,          /* No vote */

		<123 512 922 0>, <1 757 1000 0>,     /* PWM G1 */

		<123 512 1844 0>, <1 757 1000 0>,    /* PWM G2 */

		<123 512 3688 0>, <1 757 1000 0>,    /* PWM G3 */

		<123 512 7376 0>, <1 757 1000 0>,    /* PWM G4 */

		<123 512 1844 0>, <1 757 1000 0>,    /* PWM G1 L2 */

		<123 512 3688 0>, <1 757 1000 0>,    /* PWM G2 L2 */

		<123 512 7376 0>, <1 757 1000 0>,    /* PWM G3 L2 */

		<123 512 14752 0>, <1 757 1000 0>,   /* PWM G4 L2 */

		<123 512 127796 0>, <1 757 1000 0>,  /* HS G1 RA */

		<123 512 255591 0>, <1 757 1000 0>,  /* HS G2 RA */

		<123 512 2097152 0>, <1 757 102400 0>,  /* HS G3 RA */

		<123 512 255591 0>, <1 757 1000 0>,  /* HS G1 RA L2 */

		<123 512 511181 0>, <1 757 1000 0>,  /* HS G2 RA L2 */

		<123 512 4194304 0>, <1 757 204800 0>, /* HS G3 RA L2 */

		<123 512 149422 0>, <1 757 1000 0>,  /* HS G1 RB */

		<123 512 298189 0>, <1 757 1000 0>,  /* HS G2 RB */

		<123 512 2097152 0>, <1 757 102400 0>,  /* HS G3 RB */

		<123 512 298189 0>, <1 757 1000 0>,  /* HS G1 RB L2 */

		<123 512 596378 0>, <1 757 1000 0>,  /* HS G2 RB L2 */

		<123 512 4194304 0>, <1 757 204800 0>, /* HS G3 RB L2 */

		<123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */



		qcom,bus-vector-names = "MIN",

		"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",

		"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",

		"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",

		"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2",

		"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",

		"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2",

		"MAX";



		/* PM QoS */

		qcom,pm-qos-cpu-groups = <0x0f 0xf0>;

		qcom,pm-qos-cpu-group-latency-us = <70 70>;

		qcom,pm-qos-default-cpu = <0>;



		pinctrl-names = "dev-reset-assert", "dev-reset-deassert";

		pinctrl-0 = <&ufs_dev_reset_assert>;

		pinctrl-1 = <&ufs_dev_reset_deassert>;



		resets = <&clock_gcc GCC_UFS_PHY_BCR>;

		reset-names = "core_reset";



		status = "disabled";

	};



	extcon_storage_cd: extcon_storage_cd {

		compatible = "extcon-gpio";

		extcon-id = <62>; /* EXTCON_MECHANICAL */

		status = "disabled";

	};



	ufsphy_card: ufsphy_card@1da7000 {

		reg = <0x1da7000 0xda8>; /* PHY regs */

		reg-names = "phy_mem";

		#phy-cells = <0>;



		lanes-per-direction = <1>;



		status = "disabled";

	};



	ufshc_card: ufshc_card@1da4000 {

		compatible = "qcom,ufshc";

		reg = <0x1da4000 0x2500>;

		interrupts = <0 125 0>;

		phys = <&ufsphy_card>;

		phy-names = "ufsphy";



		lanes-per-direction = <1>;

		dev-ref-clk-freq = <0>; /* 19.2 MHz */



		clock-names =

			"tx_lane0_sync_clk",

			"rx_lane0_sync_clk";

		clocks =

			<&clock_gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>,

			<&clock_gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>;

		freq-table-hz =

			<0 0>,

			<0 0>;



		qcom,msm-bus,name = "ufshc_card";

		qcom,msm-bus,num-cases = <9>;

		qcom,msm-bus,num-paths = <2>;

		qcom,msm-bus,vectors-KBps =

		<122 512 0 0>, <1 756 0 0>,          /* No vote */

		<122 512 922 0>, <1 756 1000 0>,     /* PWM G1 */

		<122 512 127796 0>, <1 756 1000 0>,  /* HS G1 RA */

		<122 512 255591 0>, <1 756 1000 0>,  /* HS G2 RA */

		<122 512 2097152 0>, <1 756 102400 0>,  /* HS G3 RA */

		<122 512 149422 0>, <1 756 1000 0>,  /* HS G1 RB */

		<122 512 298189 0>, <1 756 1000 0>,  /* HS G2 RB */

		<122 512 2097152 0>, <1 756 102400 0>,  /* HS G3 RB */

		<122 512 7643136 0>, <1 756 307200 0>; /* Max. bandwidth */

		qcom,bus-vector-names = "MIN",

		"PWM_G1_L1",

		"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",

		"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",

		"MAX";



		/* PM QoS */

		qcom,pm-qos-cpu-groups = <0x0f 0xf0>;

		qcom,pm-qos-cpu-group-latency-us = <70 70>;

		qcom,pm-qos-default-cpu = <0>;



		/*

		 * Note: this instance doesn't have control over UFS device

		 * reset

		 */



		resets = <&clock_gcc GCC_UFS_CARD_BCR>;

		reset-names = "core_reset";



		status = "disabled";

	};

};



&emac_gdsc {