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Commit 33ad71d3 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "Merge remote-tracking branch 'quic/dev/msm-4.14-display' into msm-4.14"

parents 03f7065f a4defe22

Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt

+7 −0
Original line number Diff line number Diff line
@@ -187,6 +187,9 @@ Optional properties: 
					255 = default value.

- qcom,mdss-brightness-max-level:	Specifies the max brightness level supported.

					255 = default value.

- qcom,bl-update-flag:			A string that specifies controls for backlight update of the panel.

					"delay_until_first_frame" = Delay backlight update of the panel

					until the first frame is received from the HW.

- qcom,mdss-dsi-interleave-mode:	Specifies interleave mode.

					0 = default value.

- qcom,mdss-dsi-panel-type:		Specifies the panel operating mode.
@@ -529,6 +532,8 @@ Optional properties: 
					display. The first set is indexed by the

					value 0.

- qcom,mdss-dsi-ext-bridge-mode:	External bridge chip is connected instead of panel.

- qcom,mdss-dsi-dma-schedule-line:	An integer value indicates the line number after vertical active

					region, at which command DMA needs to be triggered.



Required properties for sub-nodes:	None

Optional properties:
@@ -604,6 +609,7 @@ Example: 
		qcom,mdss-dsi-bl-min-level = <1>;

		qcom,mdss-dsi-bl-max-level = < 15>;

		qcom,mdss-brightness-max-level = <255>;

		qcom,bl-update-flag = "delay_until_first_frame";

		qcom,mdss-dsi-interleave-mode = <0>;

		qcom,mdss-dsi-panel-type = "dsi_video_mode";

		qcom,mdss-dsi-te-check-enable;
@@ -786,5 +792,6 @@ Example: 
		qcom,display-topology = <1 1 1>,

			                <2 2 1>;

		qcom,default-topology-index = <0>;

		qcom,mdss-dsi-dma-schedule-line = <5>;

	};

};

arch/arm64/boot/dts/qcom/sm6150-sde-display.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -236,7 +236,7 @@ 
&dsi_hx83112a_truly_video {

	qcom,mdss-dsi-t-clk-post = <0x0e>;

	qcom,mdss-dsi-t-clk-pre = <0x31>;

	qcom,mdss-dsi-min-refresh-rate = <53>;

	qcom,mdss-dsi-min-refresh-rate = <48>;

	qcom,mdss-dsi-max-refresh-rate = <60>;

	qcom,mdss-dsi-pan-enable-dynamic-fps;

	qcom,mdss-dsi-pan-fps-update =

drivers/clk/qcom/mdss/mdss-dp-pll-14nm.c

+26 −68
Original line number Diff line number Diff line
@@ -101,7 +101,7 @@ static struct dp_pll_vco_clk dp_vco_clk = { 
};



static struct clk_fixed_factor dp_phy_pll_link_clk = {

	.div = 5,

	.div = 10,

	.mult = 1,



	.hw.init = &(struct clk_init_data){
@@ -292,6 +292,7 @@ static int dp_vco_pll_init_db_14nm(struct dp_pll_db *pdb, 
		pdb->lock_cmp2_mode0 = 0x21;

		pdb->lock_cmp3_mode0 = 0x00;

		pdb->phy_vco_div = 0x1;

		pdb->lane_mode_1 = 0xc6;

		break;

	case DP_VCO_HSCLK_RATE_2700MHZDIV1000:

		pdb->hsclk_sel = 0x24;
@@ -303,6 +304,7 @@ static int dp_vco_pll_init_db_14nm(struct dp_pll_db *pdb, 
		pdb->lock_cmp2_mode0 = 0x38;

		pdb->lock_cmp3_mode0 = 0x00;

		pdb->phy_vco_div = 0x1;

		pdb->lane_mode_1 = 0xc4;

		break;

	case DP_VCO_HSCLK_RATE_5400MHZDIV1000:

		pdb->hsclk_sel = 0x20;
@@ -314,6 +316,7 @@ static int dp_vco_pll_init_db_14nm(struct dp_pll_db *pdb, 
		pdb->lock_cmp2_mode0 = 0x70;

		pdb->lock_cmp3_mode0 = 0x00;

		pdb->phy_vco_div = 0x2;

		pdb->lane_mode_1 = 0xc4;

		break;

	default:

		return -EINVAL;
@@ -334,17 +337,7 @@ int dp_config_vco_rate_14nm(struct dp_pll_vco_clk *vco, 
		return res;

	}



	if (pdb->lane_cnt != 4) {

		if (pdb->orientation == ORIENTATION_CC2)

			MDSS_PLL_REG_W(dp_res->phy_base,

				DP_PHY_PD_CTL, 0x2d);

		else

			MDSS_PLL_REG_W(dp_res->phy_base,

				DP_PHY_PD_CTL, 0x35);

	} else {

		MDSS_PLL_REG_W(dp_res->phy_base,

			DP_PHY_PD_CTL, 0x3d);

	}

	MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_PD_CTL, 0x3d);



	/* Make sure the PHY register writes are done */

	wmb();
@@ -418,10 +411,15 @@ int dp_config_vco_rate_14nm(struct dp_pll_vco_clk *vco, 
		QSERDES_COM_CORE_CLK_EN, 0x0f);

	wmb(); /* make sure write happens */



	MDSS_PLL_REG_W(dp_res->phy_base,

		QSERDES_TX0_OFFSET + TXn_LANE_MODE_1, pdb->lane_mode_1);

	MDSS_PLL_REG_W(dp_res->phy_base,

		QSERDES_TX1_OFFSET + TXn_LANE_MODE_1, pdb->lane_mode_1);



	if (pdb->orientation == ORIENTATION_CC2)

		MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_MODE, 0xc8);

		MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_MODE, 0xc9);

	else

		MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_MODE, 0xd8);

		MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_MODE, 0xd9);

	wmb(); /* make sure write happens */



	/* TX Lane configuration */
@@ -546,10 +544,8 @@ static bool dp_14nm_phy_rdy_status(struct mdss_pll_resources *dp_res) 
static int dp_pll_enable_14nm(struct clk_hw *hw)

{

	int rc = 0;

	u32 bias_en, drvr_en;

	struct dp_pll_vco_clk *vco = to_dp_vco_hw(hw);

	struct mdss_pll_resources *dp_res = vco->priv;

	struct dp_pll_db *pdb = (struct dp_pll_db *)dp_res->priv;



	MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_CFG, 0x01);

	MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_CFG, 0x05);
@@ -580,36 +576,14 @@ static int dp_pll_enable_14nm(struct clk_hw *hw) 


	pr_debug("PLL is locked\n");



	if (pdb->lane_cnt == 1) {

		bias_en = 0x3e;

		drvr_en = 0x13;

	} else {

		bias_en = 0x3f;

		drvr_en = 0x10;

	}



	if (pdb->lane_cnt != 4) {

		if (pdb->orientation == ORIENTATION_CC1) {

	MDSS_PLL_REG_W(dp_res->phy_base,

			QSERDES_TX1_OFFSET + TXn_TRANSCEIVER_BIAS_EN, bias_en);

		QSERDES_TX0_OFFSET + TXn_TRANSCEIVER_BIAS_EN, 0x3f);

	MDSS_PLL_REG_W(dp_res->phy_base,

			QSERDES_TX1_OFFSET + TXn_HIGHZ_DRVR_EN, drvr_en);

		} else {

		QSERDES_TX0_OFFSET + TXn_HIGHZ_DRVR_EN, 0x10);

	MDSS_PLL_REG_W(dp_res->phy_base,

			QSERDES_TX0_OFFSET + TXn_TRANSCEIVER_BIAS_EN, bias_en);

		QSERDES_TX1_OFFSET + TXn_TRANSCEIVER_BIAS_EN, 0x3f);

	MDSS_PLL_REG_W(dp_res->phy_base,

			QSERDES_TX0_OFFSET + TXn_HIGHZ_DRVR_EN, drvr_en);

		}

	} else {

		MDSS_PLL_REG_W(dp_res->phy_base,

			QSERDES_TX0_OFFSET + TXn_TRANSCEIVER_BIAS_EN, bias_en);

		MDSS_PLL_REG_W(dp_res->phy_base,

			QSERDES_TX0_OFFSET + TXn_HIGHZ_DRVR_EN, drvr_en);

		MDSS_PLL_REG_W(dp_res->phy_base,

			QSERDES_TX1_OFFSET + TXn_TRANSCEIVER_BIAS_EN, bias_en);

		MDSS_PLL_REG_W(dp_res->phy_base,

			QSERDES_TX1_OFFSET + TXn_HIGHZ_DRVR_EN, drvr_en);

	}

		QSERDES_TX1_OFFSET + TXn_HIGHZ_DRVR_EN, 0x10);



	MDSS_PLL_REG_W(dp_res->phy_base,

		QSERDES_TX0_OFFSET + TXn_TX_POL_INV, 0x0a);
@@ -739,7 +713,7 @@ unsigned long dp_vco_recalc_rate_14nm(struct clk_hw *hw, 
{

	struct dp_pll_vco_clk *vco = to_dp_vco_hw(hw);

	int rc;

	u32 div, hsclk_div, link2xclk_div = 0;

	u32 div, hsclk_div;

	u64 vco_rate;

	struct mdss_pll_resources *dp_res = vco->priv;
@@ -766,28 +740,12 @@ unsigned long dp_vco_recalc_rate_14nm(struct clk_hw *hw, 
		hsclk_div = 5;

	}



	div = MDSS_PLL_REG_R(dp_res->phy_base, DP_PHY_MODE);



	if (div & 0xd8)

		pr_err("DP PAR Rate not correct\n");



	if ((div & 0x3) == 1)

		link2xclk_div = 10;

	else if ((div & 0x3) == 0)

		link2xclk_div = 5;

	else

		pr_err("unsupported div. Phy_mode: %d\n", div);



	if (link2xclk_div == 10) {

		vco_rate = DP_VCO_HSCLK_RATE_2700MHZDIV1000;

	} else {

	if (hsclk_div == 5)

		vco_rate = DP_VCO_HSCLK_RATE_1620MHZDIV1000;

	else if (hsclk_div == 3)

		vco_rate = DP_VCO_HSCLK_RATE_2700MHZDIV1000;

	else

		vco_rate = DP_VCO_HSCLK_RATE_5400MHZDIV1000;

	}



	pr_debug("returning vco rate = %lu\n", (unsigned long)vco_rate);

drivers/clk/qcom/mdss/mdss-dp-pll-14nm.h

+3 −0
Original line number Diff line number Diff line
@@ -176,6 +176,9 @@ struct dp_pll_db { 


	/* PHY vco divider */

	u32 phy_vco_div;



	/* TX settings */

	u32 lane_mode_1;

};



int dp_vco_set_rate_14nm(struct clk_hw *hw, unsigned long rate,

drivers/gpu/drm/msm/dp/dp_catalog.c

+6 −1
Original line number Diff line number Diff line
@@ -703,7 +703,7 @@ static void dp_catalog_ctrl_state_ctrl(struct dp_catalog_ctrl *ctrl, u32 state) 
	wmb();

}



static void dp_catalog_ctrl_config_ctrl(struct dp_catalog_ctrl *ctrl)

static void dp_catalog_ctrl_config_ctrl(struct dp_catalog_ctrl *ctrl, u8 ln_cnt)

{

	struct dp_catalog_private *catalog;

	struct dp_io_data *io_data;
@@ -717,6 +717,11 @@ static void dp_catalog_ctrl_config_ctrl(struct dp_catalog_ctrl *ctrl) 
	catalog = dp_catalog_get_priv(ctrl);

	io_data = catalog->io.dp_link;



	cfg = dp_read(catalog->exe_mode, io_data, DP_CONFIGURATION_CTRL);

	cfg &= ~(BIT(4) | BIT(5));

	cfg |= (ln_cnt - 1) << 4;

	dp_write(catalog->exe_mode, io_data, DP_CONFIGURATION_CTRL, cfg);



	cfg = dp_read(catalog->exe_mode, io_data, DP_MAINLINK_CTRL);

	cfg |= 0x02000000;

	dp_write(catalog->exe_mode, io_data, DP_MAINLINK_CTRL, cfg);