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Commit 3351047f authored by Paul Burton's avatar Paul Burton Committed by Ralf Baechle
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MIPS: Simplify PTRACE_PEEKUSR for FPC_EIR 



All architecturally defined bits in the FPU implementation register
are read only & unchanging. It contains some implementation-defined
bits but the architecture manual states "This bits are explicitly not
intended to be used for mode control functions" which seems to provide
justification for viewing the register as a whole as unchanging. This
being the case we can simply re-use the value we read at boot rather
than having to re-read it later, and avoid the complexity which that
read entails.

Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
Reviewed-by: default avatarQais Yousef <qais.yousef@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6144/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent d7b12056

arch/mips/kernel/ptrace.c

+3 −37
Original line number Original line Diff line number Diff line
@@ -501,44 +501,10 @@ long arch_ptrace(struct task_struct *child, long request, 
		case FPC_CSR:

		case FPC_CSR:

			tmp = child->thread.fpu.fcr31;

			tmp = child->thread.fpu.fcr31;

			break;

			break;

		case FPC_EIR: { /* implementation / version register */

		case FPC_EIR:

			unsigned int flags;

			/* implementation / version register */

#ifdef CONFIG_MIPS_MT_SMTC

			tmp = current_cpu_data.fpu_id;

			unsigned long irqflags;

			unsigned int mtflags;

#endif /* CONFIG_MIPS_MT_SMTC */



			preempt_disable();

			if (!cpu_has_fpu) {

				preempt_enable();

				break;

			}



#ifdef CONFIG_MIPS_MT_SMTC

			/* Read-modify-write of Status must be atomic */

			local_irq_save(irqflags);

			mtflags = dmt();

#endif /* CONFIG_MIPS_MT_SMTC */

			if (cpu_has_mipsmt) {

				unsigned int vpflags = dvpe();

				flags = read_c0_status();

				__enable_fpu(FPU_AS_IS);

				__asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));

				write_c0_status(flags);

				evpe(vpflags);

			} else {

				flags = read_c0_status();

				__enable_fpu(FPU_AS_IS);

				__asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));

				write_c0_status(flags);

			}

#ifdef CONFIG_MIPS_MT_SMTC

			emt(mtflags);

			local_irq_restore(irqflags);

#endif /* CONFIG_MIPS_MT_SMTC */

			preempt_enable();

			break;

			break;

		}

		case DSP_BASE ... DSP_BASE + 5: {

		case DSP_BASE ... DSP_BASE + 5: {

			dspreg_t *dregs;

			dspreg_t *dregs;

arch/mips/kernel/ptrace32.c

+3 −39
Original line number Original line Diff line number Diff line
@@ -127,46 +127,10 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, 
		case FPC_CSR:

		case FPC_CSR:

			tmp = child->thread.fpu.fcr31;

			tmp = child->thread.fpu.fcr31;

			break;

			break;

		case FPC_EIR: { /* implementation / version register */

		case FPC_EIR:

			unsigned int flags;

			/* implementation / version register */

#ifdef CONFIG_MIPS_MT_SMTC

			tmp = current_cpu_data.fpu_id;

			unsigned int irqflags;

			unsigned int mtflags;

#endif /* CONFIG_MIPS_MT_SMTC */



			preempt_disable();

			if (!cpu_has_fpu) {

				preempt_enable();

				tmp = 0;

				break;

			}



#ifdef CONFIG_MIPS_MT_SMTC

			/* Read-modify-write of Status must be atomic */

			local_irq_save(irqflags);

			mtflags = dmt();

#endif /* CONFIG_MIPS_MT_SMTC */



			if (cpu_has_mipsmt) {

				unsigned int vpflags = dvpe();

				flags = read_c0_status();

				__enable_fpu(FPU_AS_IS);

				__asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));

				write_c0_status(flags);

				evpe(vpflags);

			} else {

				flags = read_c0_status();

				__enable_fpu(FPU_AS_IS);

				__asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));

				write_c0_status(flags);

			}

#ifdef CONFIG_MIPS_MT_SMTC

			emt(mtflags);

			local_irq_restore(irqflags);

#endif /* CONFIG_MIPS_MT_SMTC */

			preempt_enable();

			break;

			break;

		}

		case DSP_BASE ... DSP_BASE + 5: {

		case DSP_BASE ... DSP_BASE + 5: {

			dspreg_t *dregs;

			dspreg_t *dregs;