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Commit 3301e7c5 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge changes I3a31b61b,I8d683b7b into msm-4.14 

* changes:
  ARM: dts: msm: Add GPUCC debug clock for sdm855
  clk: qcom: Add clock measurement support for GPUCC for sdm855
parents 738198e8 ed2bd5bb

arch/arm64/boot/dts/qcom/sdm855.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -1344,7 +1344,7 @@ 
	};



	clock_gpucc: qcom,gpucc {

		compatible = "qcom,gpucc-sdm855";

		compatible = "qcom,gpucc-sdm855", "syscon";

		reg = <0x2c90000 0x9000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&pm855l_s6_level>;
@@ -1373,6 +1373,7 @@ 
		qcom,camcc = <&clock_camcc>;

		qcom,dispcc = <&clock_dispcc>;

		qcom,npucc = <&clock_npucc>;

		qcom,gpucc = <&clock_gpucc>;

		clock-names = "xo_clk_src";

		clocks = <&clock_rpmh RPMH_CXO_CLK>;

		#clock-cells = <1>;

drivers/clk/qcom/debugcc-sdm855.c

+52 −0
Original line number Diff line number Diff line
@@ -266,6 +266,22 @@ static const char *const debug_mux_parent_names[] = { 
	"gcc_video_axi1_clk",

	"gcc_video_axic_clk",

	"gcc_video_xo_clk",

	"gpu_cc_acd_ahb_clk",

	"gpu_cc_acd_cxo_clk",

	"gpu_cc_ahb_clk",

	"gpu_cc_crc_ahb_clk",

	"gpu_cc_cx_apb_clk",

	"gpu_cc_cx_gmu_clk",

	"gpu_cc_cx_qdss_at_clk",

	"gpu_cc_cx_qdss_trig_clk",

	"gpu_cc_cx_qdss_tsctr_clk",

	"gpu_cc_cx_snoc_dvm_clk",

	"gpu_cc_cxo_aon_clk",

	"gpu_cc_cxo_clk",

	"gpu_cc_gx_gmu_clk",

	"gpu_cc_gx_qdss_tsctr_clk",

	"gpu_cc_gx_vsense_clk",

	"gpu_cc_sleep_clk",

	"npu_cc_armwic_core_clk",

	"npu_cc_bto_core_clk",

	"npu_cc_bwmon_clk",
@@ -766,6 +782,38 @@ static struct clk_debug_mux gcc_debug_mux = { 
			0x4C, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x62004, 0x62008 },

		{ "gcc_video_xo_clk", 0x51, 1, GCC,

			0x51, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x62004, 0x62008 },

		{ "gpu_cc_acd_ahb_clk", 0x162, 1, GPU_CC,

			0x20, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 },

		{ "gpu_cc_acd_cxo_clk", 0x162, 1, GPU_CC,

			0x1F, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 },

		{ "gpu_cc_ahb_clk", 0x162, 1, GPU_CC,

			0x10, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 },

		{ "gpu_cc_crc_ahb_clk", 0x162, 1, GPU_CC,

			0x11, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 },

		{ "gpu_cc_cx_apb_clk", 0x162, 1, GPU_CC,

			0x14, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 },

		{ "gpu_cc_cx_gmu_clk", 0x162, 1, GPU_CC,

			0x18, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 },

		{ "gpu_cc_cx_qdss_at_clk", 0x162, 1, GPU_CC,

			0x12, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 },

		{ "gpu_cc_cx_qdss_trig_clk", 0x162, 1, GPU_CC,

			0x17, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 },

		{ "gpu_cc_cx_qdss_tsctr_clk", 0x162, 1, GPU_CC,

			0x13, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 },

		{ "gpu_cc_cx_snoc_dvm_clk", 0x162, 1, GPU_CC,

			0x15, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 },

		{ "gpu_cc_cxo_aon_clk", 0x162, 1, GPU_CC,

			0xA, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 },

		{ "gpu_cc_cxo_clk", 0x162, 1, GPU_CC,

			0x19, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 },

		{ "gpu_cc_gx_gmu_clk", 0x162, 1, GPU_CC,

			0xF, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 },

		{ "gpu_cc_gx_qdss_tsctr_clk", 0x162, 1, GPU_CC,

			0xD, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 },

		{ "gpu_cc_gx_vsense_clk", 0x162, 1, GPU_CC,

			0xC, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 },

		{ "gpu_cc_sleep_clk", 0x162, 1, GPU_CC,

			0x16, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 },

		{ "npu_cc_armwic_core_clk", 0x180, 1, NPU_CC,

			0x4, 0xFF, 0, 0x3, 0, 2, 0x4000, 0x3004, 0x3008 },

		{ "npu_cc_bto_core_clk", 0x180, 1, NPU_CC,
@@ -880,6 +928,10 @@ static int clk_debug_sdm855_probe(struct platform_device *pdev) 
	if (ret)

		return ret;



	ret = map_debug_bases(pdev, "qcom,gpucc", GPU_CC);

	if (ret)

		return ret;



	clk = devm_clk_register(&pdev->dev, &gcc_debug_mux.hw);

	if (IS_ERR(clk)) {

		dev_err(&pdev->dev, "Unable to register GCC debug mux\n");