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Commit 3258943d authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-for-v4.10-rc6' of git://people.freedesktop.org/~airlied/linux 

Pull drm fixes from Dave Airlie:
 "drm fixes across the board.

  Okay holidays and LCA kinda caught up with me, I thought I'd get some
  of this dequeued last week, but Hobart was sunny and warm and not all
  gloomy and rainy as usual.

  This is a bit large, but not too much considering it's two weeks stuff
  from AMD and Intel.

  core:
   - one locking fix that helps with dynamic suspend/resume races

  i915:
   - mostly GVT updates, GVT was a recent introduction so fixes for it
     shouldn't cause any notable side effects.

  amdgpu:
   - a bunch of fixes for GPUs with a different memory controller design
     that need different firmware.

  exynos:
   - decon regression fixes

  msm:
   - two regression fixes

  etnaviv:
   - a workaround for an mmu bug that needs a lot more work.

  virtio:
   - sparse fix, and a maintainers update"

* tag 'drm-fixes-for-v4.10-rc6' of git://people.freedesktop.org/~airlied/linux: (56 commits)
  drm/exynos/decon5433: set STANDALONE_UPDATE_F on output enablement
  drm/exynos/decon5433: fix CMU programming
  drm/exynos/decon5433: do not disable video after reset
  drm/i915: Ignore bogus plane coordinates on SKL when the plane is not visible
  drm/i915: Remove WaDisableLSQCROPERFforOCL KBL workaround.
  drm/amdgpu: add support for new hainan variants
  drm/radeon: add support for new hainan variants
  drm/amdgpu: change clock gating mode for uvd_v4.
  drm/amdgpu: fix program vce instance logic error.
  drm/amdgpu: fix bug set incorrect value to vce register
  Revert "drm/amdgpu: Only update the CUR_SIZE register when necessary"
  drm/msm: fix potential null ptr issue in non-iommu case
  drm/msm/mdp5: rip out plane->pending tracking
  drm/exynos/decon5433: set STANDALONE_UPDATE_F also if planes are disabled
  drm/exynos/decon5433: update shadow registers iff there are active windows
  drm/i915/gvt: rewrite gt reset handler using new function intel_gvt_reset_vgpu_locked
  drm/i915/gvt: fix vGPU instance reuse issues by vGPU reset function
  drm/i915/gvt: introduce intel_vgpu_reset_mmio() to reset mmio space
  drm/i915/gvt: move mmio init/clean function to mmio.c
  drm/i915/gvt: introduce intel_vgpu_reset_cfg_space to reset configuration space
  ...
parents 7a308bb3 93279010

MAINTAINERS

+13 −3
Original line number Diff line number Diff line
@@ -4100,12 +4100,18 @@ F: drivers/gpu/drm/bridge/ 


DRM DRIVER FOR BOCHS VIRTUAL GPU

M:	Gerd Hoffmann <kraxel@redhat.com>

S:	Odd Fixes

L:	virtualization@lists.linux-foundation.org

T:	git git://git.kraxel.org/linux drm-qemu

S:	Maintained

F:	drivers/gpu/drm/bochs/



DRM DRIVER FOR QEMU'S CIRRUS DEVICE

M:	Dave Airlie <airlied@redhat.com>

S:	Odd Fixes

M:	Gerd Hoffmann <kraxel@redhat.com>

L:	virtualization@lists.linux-foundation.org

T:	git git://git.kraxel.org/linux drm-qemu

S:	Obsolete

W:	https://www.kraxel.org/blog/2014/10/qemu-using-cirrus-considered-harmful/

F:	drivers/gpu/drm/cirrus/



RADEON and AMDGPU DRM DRIVERS
@@ -4298,7 +4304,10 @@ F: Documentation/devicetree/bindings/display/renesas,du.txt 


DRM DRIVER FOR QXL VIRTUAL GPU

M:	Dave Airlie <airlied@redhat.com>

S:	Odd Fixes

M:	Gerd Hoffmann <kraxel@redhat.com>

L:	virtualization@lists.linux-foundation.org

T:	git git://git.kraxel.org/linux drm-qemu

S:	Maintained

F:	drivers/gpu/drm/qxl/

F:	include/uapi/drm/qxl_drm.h
@@ -13092,6 +13101,7 @@ M: David Airlie <airlied@linux.ie> 
M:	Gerd Hoffmann <kraxel@redhat.com>

L:	dri-devel@lists.freedesktop.org

L:	virtualization@lists.linux-foundation.org

T:	git git://git.kraxel.org/linux drm-qemu

S:	Maintained

F:	drivers/gpu/drm/virtio/

F:	include/uapi/linux/virtio_gpu.h

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

+7 −15
Original line number Diff line number Diff line
@@ -2512,6 +2512,8 @@ static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc, 


	WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);

	WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);

	WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,

	       ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));



	return 0;

}
@@ -2537,7 +2539,6 @@ static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc, 
				      int32_t hot_y)

{

	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

	struct amdgpu_device *adev = crtc->dev->dev_private;

	struct drm_gem_object *obj;

	struct amdgpu_bo *aobj;

	int ret;
@@ -2578,7 +2579,9 @@ static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc, 


	dce_v10_0_lock_cursor(crtc, true);



	if (hot_x != amdgpu_crtc->cursor_hot_x ||

	if (width != amdgpu_crtc->cursor_width ||

	    height != amdgpu_crtc->cursor_height ||

	    hot_x != amdgpu_crtc->cursor_hot_x ||

	    hot_y != amdgpu_crtc->cursor_hot_y) {

		int x, y;
@@ -2587,16 +2590,10 @@ static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc, 


		dce_v10_0_cursor_move_locked(crtc, x, y);



		amdgpu_crtc->cursor_hot_x = hot_x;

		amdgpu_crtc->cursor_hot_y = hot_y;

	}



	if (width != amdgpu_crtc->cursor_width ||

	    height != amdgpu_crtc->cursor_height) {

		WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,

		       (width - 1) << 16 | (height - 1));

		amdgpu_crtc->cursor_width = width;

		amdgpu_crtc->cursor_height = height;

		amdgpu_crtc->cursor_hot_x = hot_x;

		amdgpu_crtc->cursor_hot_y = hot_y;

	}



	dce_v10_0_show_cursor(crtc);
@@ -2620,7 +2617,6 @@ static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc, 
static void dce_v10_0_cursor_reset(struct drm_crtc *crtc)

{

	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

	struct amdgpu_device *adev = crtc->dev->dev_private;



	if (amdgpu_crtc->cursor_bo) {

		dce_v10_0_lock_cursor(crtc, true);
@@ -2628,10 +2624,6 @@ static void dce_v10_0_cursor_reset(struct drm_crtc *crtc) 
		dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,

					     amdgpu_crtc->cursor_y);



		WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,

		       (amdgpu_crtc->cursor_width - 1) << 16 |

		       (amdgpu_crtc->cursor_height - 1));



		dce_v10_0_show_cursor(crtc);



		dce_v10_0_lock_cursor(crtc, false);

drivers/gpu/drm/amd/amdgpu/dce_v11_0.c

+7 −15
Original line number Diff line number Diff line
@@ -2532,6 +2532,8 @@ static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc, 


	WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);

	WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);

	WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,

	       ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));



	return 0;

}
@@ -2557,7 +2559,6 @@ static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc, 
				      int32_t hot_y)

{

	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

	struct amdgpu_device *adev = crtc->dev->dev_private;

	struct drm_gem_object *obj;

	struct amdgpu_bo *aobj;

	int ret;
@@ -2598,7 +2599,9 @@ static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc, 


	dce_v11_0_lock_cursor(crtc, true);



	if (hot_x != amdgpu_crtc->cursor_hot_x ||

	if (width != amdgpu_crtc->cursor_width ||

	    height != amdgpu_crtc->cursor_height ||

	    hot_x != amdgpu_crtc->cursor_hot_x ||

	    hot_y != amdgpu_crtc->cursor_hot_y) {

		int x, y;
@@ -2607,16 +2610,10 @@ static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc, 


		dce_v11_0_cursor_move_locked(crtc, x, y);



		amdgpu_crtc->cursor_hot_x = hot_x;

		amdgpu_crtc->cursor_hot_y = hot_y;

	}



	if (width != amdgpu_crtc->cursor_width ||

	    height != amdgpu_crtc->cursor_height) {

		WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,

		       (width - 1) << 16 | (height - 1));

		amdgpu_crtc->cursor_width = width;

		amdgpu_crtc->cursor_height = height;

		amdgpu_crtc->cursor_hot_x = hot_x;

		amdgpu_crtc->cursor_hot_y = hot_y;

	}



	dce_v11_0_show_cursor(crtc);
@@ -2640,7 +2637,6 @@ static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc, 
static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)

{

	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

	struct amdgpu_device *adev = crtc->dev->dev_private;



	if (amdgpu_crtc->cursor_bo) {

		dce_v11_0_lock_cursor(crtc, true);
@@ -2648,10 +2644,6 @@ static void dce_v11_0_cursor_reset(struct drm_crtc *crtc) 
		dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,

					     amdgpu_crtc->cursor_y);



		WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,

		       (amdgpu_crtc->cursor_width - 1) << 16 |

		       (amdgpu_crtc->cursor_height - 1));



		dce_v11_0_show_cursor(crtc);



		dce_v11_0_lock_cursor(crtc, false);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

+9 −15
Original line number Diff line number Diff line
@@ -1859,6 +1859,8 @@ static int dce_v6_0_cursor_move_locked(struct drm_crtc *crtc, 
	struct amdgpu_device *adev = crtc->dev->dev_private;

	int xorigin = 0, yorigin = 0;



	int w = amdgpu_crtc->cursor_width;



	amdgpu_crtc->cursor_x = x;

	amdgpu_crtc->cursor_y = y;
@@ -1878,6 +1880,8 @@ static int dce_v6_0_cursor_move_locked(struct drm_crtc *crtc, 


	WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);

	WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);

	WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,

	       ((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1));



	return 0;

}
@@ -1903,7 +1907,6 @@ static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc, 
				     int32_t hot_y)

{

	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

	struct amdgpu_device *adev = crtc->dev->dev_private;

	struct drm_gem_object *obj;

	struct amdgpu_bo *aobj;

	int ret;
@@ -1944,7 +1947,9 @@ static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc, 


	dce_v6_0_lock_cursor(crtc, true);



	if (hot_x != amdgpu_crtc->cursor_hot_x ||

	if (width != amdgpu_crtc->cursor_width ||

	    height != amdgpu_crtc->cursor_height ||

	    hot_x != amdgpu_crtc->cursor_hot_x ||

	    hot_y != amdgpu_crtc->cursor_hot_y) {

		int x, y;
@@ -1953,16 +1958,10 @@ static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc, 


		dce_v6_0_cursor_move_locked(crtc, x, y);



		amdgpu_crtc->cursor_hot_x = hot_x;

		amdgpu_crtc->cursor_hot_y = hot_y;

	}



	if (width != amdgpu_crtc->cursor_width ||

	    height != amdgpu_crtc->cursor_height) {

		WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,

		       (width - 1) << 16 | (height - 1));

		amdgpu_crtc->cursor_width = width;

		amdgpu_crtc->cursor_height = height;

		amdgpu_crtc->cursor_hot_x = hot_x;

		amdgpu_crtc->cursor_hot_y = hot_y;

	}



	dce_v6_0_show_cursor(crtc);
@@ -1986,7 +1985,6 @@ static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc, 
static void dce_v6_0_cursor_reset(struct drm_crtc *crtc)

{

	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

	struct amdgpu_device *adev = crtc->dev->dev_private;



	if (amdgpu_crtc->cursor_bo) {

		dce_v6_0_lock_cursor(crtc, true);
@@ -1994,10 +1992,6 @@ static void dce_v6_0_cursor_reset(struct drm_crtc *crtc) 
		dce_v6_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,

					    amdgpu_crtc->cursor_y);



		WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,

		       (amdgpu_crtc->cursor_width - 1) << 16 |

		       (amdgpu_crtc->cursor_height - 1));



		dce_v6_0_show_cursor(crtc);

		dce_v6_0_lock_cursor(crtc, false);

	}

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

+7 −15
Original line number Diff line number Diff line
@@ -2363,6 +2363,8 @@ static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc, 


	WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);

	WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);

	WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,

	       ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));



	return 0;

}
@@ -2388,7 +2390,6 @@ static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc, 
				     int32_t hot_y)

{

	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

	struct amdgpu_device *adev = crtc->dev->dev_private;

	struct drm_gem_object *obj;

	struct amdgpu_bo *aobj;

	int ret;
@@ -2429,7 +2430,9 @@ static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc, 


	dce_v8_0_lock_cursor(crtc, true);



	if (hot_x != amdgpu_crtc->cursor_hot_x ||

	if (width != amdgpu_crtc->cursor_width ||

	    height != amdgpu_crtc->cursor_height ||

	    hot_x != amdgpu_crtc->cursor_hot_x ||

	    hot_y != amdgpu_crtc->cursor_hot_y) {

		int x, y;
@@ -2438,16 +2441,10 @@ static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc, 


		dce_v8_0_cursor_move_locked(crtc, x, y);



		amdgpu_crtc->cursor_hot_x = hot_x;

		amdgpu_crtc->cursor_hot_y = hot_y;

	}



	if (width != amdgpu_crtc->cursor_width ||

	    height != amdgpu_crtc->cursor_height) {

		WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,

		       (width - 1) << 16 | (height - 1));

		amdgpu_crtc->cursor_width = width;

		amdgpu_crtc->cursor_height = height;

		amdgpu_crtc->cursor_hot_x = hot_x;

		amdgpu_crtc->cursor_hot_y = hot_y;

	}



	dce_v8_0_show_cursor(crtc);
@@ -2471,7 +2468,6 @@ static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc, 
static void dce_v8_0_cursor_reset(struct drm_crtc *crtc)

{

	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

	struct amdgpu_device *adev = crtc->dev->dev_private;



	if (amdgpu_crtc->cursor_bo) {

		dce_v8_0_lock_cursor(crtc, true);
@@ -2479,10 +2475,6 @@ static void dce_v8_0_cursor_reset(struct drm_crtc *crtc) 
		dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,

					    amdgpu_crtc->cursor_y);



		WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,

		       (amdgpu_crtc->cursor_width - 1) << 16 |

		       (amdgpu_crtc->cursor_height - 1));



		dce_v8_0_show_cursor(crtc);



		dce_v8_0_lock_cursor(crtc, false);