Merge branches 'ftrace', 'gic', 'io', 'kexec', 'mod', 'sa11x0', 'sh' and 'versatile' into devel (31edf274) · Commits · e / devices / android_kernel_oneplus_sm8150

arch/arm/Kconfig

+21 −1

Original line number	Diff line number	Diff line
		@@ -23,6 +23,7 @@ config ARM
		select PERF_USE_VMALLOC
		select HAVE_REGS_AND_STACK_ACCESS_API
		select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 \|\| CPU_V7))
		select HAVE_C_RECORDMCOUNT
		help
		The ARM series is a line of low-power-consumption RISC chip designs
		licensed by ARM Ltd and targeted at embedded applications and
		@@ -1164,7 +1165,7 @@ config ISA_DMA_API
		bool

		config PCI
		bool "PCI support" if ARCH_INTEGRATOR_AP \|\| ARCH_VERSATILE_PB \|\| ARCH_IXP4XX \|\| ARCH_KS8695 \|\| MACH_ARMCORE \|\| ARCH_CNS3XXX
		bool "PCI support" if ARCH_INTEGRATOR_AP \|\| ARCH_VERSATILE_PB \|\| ARCH_IXP4XX \|\| ARCH_KS8695 \|\| MACH_ARMCORE \|\| ARCH_CNS3XXX \|\| SA1100_NANOENGINE
		help
		Find out whether you have a PCI motherboard. PCI is the name of a
		bus system, i.e. the way the CPU talks to the other stuff inside
		@@ -1175,6 +1176,12 @@ config PCI_DOMAINS
		bool
		depends on PCI

		config PCI_NANOENGINE
		bool "BSE nanoEngine PCI support"
		depends on SA1100_NANOENGINE
		help
		Enable PCI on the BSE nanoEngine board.

		config PCI_SYSCALL
		def_bool PCI

		@@ -1650,6 +1657,19 @@ config ATAGS_PROC
		Should the atags used to boot the kernel be exported in an "atags"
		file in procfs. Useful with kexec.

		config CRASH_DUMP
		bool "Build kdump crash kernel (EXPERIMENTAL)"
		depends on EXPERIMENTAL
		help
		Generate crash dump after being started by kexec. This should
		be normally only set in special crash dump kernels which are
		loaded in the main kernel with kexec-tools into a specially
		reserved region and then later executed after a crash by
		kdump/kexec. The crash dump kernel must be compiled to a
		memory address not used by the main kernel

		For more details see Documentation/kdump/kdump.txt

		config AUTO_ZRELADDR
		bool "Auto calculation of the decompressed kernel image address"
		depends on !ZBOOT_ROM && !ARCH_U300

arch/arm/boot/compressed/Makefile

+4 −0

Original line number	Diff line number	Diff line
		@@ -45,6 +45,10 @@ else
		endif
		endif

		ifeq ($(CONFIG_ARCH_SHMOBILE),y)
		OBJS += head-shmobile.o
		endif

		#
		# We now have a PIC decompressor implementation. Decompressors running
		# from RAM should not define ZTEXTADDR. Decompressors running directly

arch/arm/boot/compressed/head-shmobile.S

0 → 100644

+53 −0

Original line number	Diff line number	Diff line
		/*
		* The head-file for SH-Mobile ARM platforms
		*
		* Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
		* Simon Horman <horms@verge.net.au>
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License as published by
		* the Free Software Foundation; version 2 of the License.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*
		* You should have received a copy of the GNU General Public License
		* along with this program; if not, write to the Free Software
		* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
		*/

		#ifdef CONFIG_ZBOOT_ROM

		.section ".start", "ax"

		/* load board-specific initialization code */
		#include <mach/zboot.h>

		b 1f
		__atags:@ tag #1
		.long 12 @ tag->hdr.size = tag_size(tag_core);
		.long 0x54410001 @ tag->hdr.tag = ATAG_CORE;
		.long 0 @ tag->u.core.flags = 0;
		.long 0 @ tag->u.core.pagesize = 0;
		.long 0 @ tag->u.core.rootdev = 0;
		@ tag #2
		.long 8 @ tag->hdr.size = tag_size(tag_mem32);
		.long 0x54410002 @ tag->hdr.tag = ATAG_MEM;
		.long CONFIG_MEMORY_SIZE @ tag->u.mem.size = CONFIG_MEMORY_SIZE;
		.long CONFIG_MEMORY_START @ @ tag->u.mem.start = CONFIG_MEMORY_START;
		@ tag #3
		.long 0 @ tag->hdr.size = 0
		.long 0 @ tag->hdr.tag = ATAG_NONE;
		1:

		/* Set board ID necessary for boot */
		ldr r7, 1f @ Set machine type register
		adr r8, __atags @ Set atag register
		b 2f

		1 : .long MACH_TYPE
		2 :

		#endif /* CONFIG_ZBOOT_ROM */

arch/arm/common/Makefile

+1 −0

Original line number	Diff line number	Diff line
		@@ -17,3 +17,4 @@ obj-$(CONFIG_ARCH_IXP2000) += uengine.o
		obj-$(CONFIG_ARCH_IXP23XX) += uengine.o
		obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o
		obj-$(CONFIG_COMMON_CLKDEV) += clkdev.o
		obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o

arch/arm/common/gic.c

+48 −21

Original line number	Diff line number	Diff line
		@@ -35,6 +35,9 @@

		static DEFINE_SPINLOCK(irq_controller_lock);

		/* Address of GIC 0 CPU interface */
		void __iomem *gic_cpu_base_addr __read_mostly;

		struct gic_chip_data {
		unsigned int irq_offset;
		void __iomem *dist_base;
		@@ -45,7 +48,7 @@ struct gic_chip_data {
		#define MAX_GIC_NR 1
		#endif

		static struct gic_chip_data gic_data[MAX_GIC_NR];
		static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;

		static inline void __iomem *gic_dist_base(unsigned int irq)
		{
		@@ -213,21 +216,16 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
		set_irq_chained_handler(irq, gic_handle_cascade_irq);
		}

		void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
		static void __init gic_dist_init(struct gic_chip_data *gic,
		unsigned int irq_start)
		{
		unsigned int gic_irqs, irq_limit, i;
		void __iomem *base = gic->dist_base;
		u32 cpumask = 1 << smp_processor_id();

		if (gic_nr >= MAX_GIC_NR)
		BUG();

		cpumask \|= cpumask << 8;
		cpumask \|= cpumask << 16;

		gic_data[gic_nr].dist_base = base;
		gic_data[gic_nr].irq_offset = (irq_start - 1) & ~31;

		writel(0, base + GIC_DIST_CTRL);

		/*
		@@ -267,7 +265,7 @@ void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
		/*
		* Limit number of interrupts registered to the platform maximum
		*/
		irq_limit = gic_data[gic_nr].irq_offset + gic_irqs;
		irq_limit = gic->irq_offset + gic_irqs;
		if (WARN_ON(irq_limit > NR_IRQS))
		irq_limit = NR_IRQS;

		@@ -276,7 +274,7 @@ void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
		*/
		for (i = irq_start; i < irq_limit; i++) {
		set_irq_chip(i, &gic_chip);
		set_irq_chip_data(i, &gic_data[gic_nr]);
		set_irq_chip_data(i, gic);
		set_irq_handler(i, handle_level_irq);
		set_irq_flags(i, IRQF_VALID \| IRQF_PROBE);
		}
		@@ -284,19 +282,12 @@ void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
		writel(1, base + GIC_DIST_CTRL);
		}

		void __cpuinit gic_cpu_init(unsigned int gic_nr, void __iomem *base)
		static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
		{
		void __iomem *dist_base;
		void __iomem *dist_base = gic->dist_base;
		void __iomem *base = gic->cpu_base;
		int i;

		if (gic_nr >= MAX_GIC_NR)
		BUG();

		dist_base = gic_data[gic_nr].dist_base;
		BUG_ON(!dist_base);

		gic_data[gic_nr].cpu_base = base;

		/*
		* Deal with the banked PPI and SGI interrupts - disable all
		* PPI interrupts, ensure all SGI interrupts are enabled.
		@@ -314,6 +305,42 @@ void __cpuinit gic_cpu_init(unsigned int gic_nr, void __iomem *base)
		writel(1, base + GIC_CPU_CTRL);
		}

		void __init gic_init(unsigned int gic_nr, unsigned int irq_start,
		void __iomem dist_base, void __iomem cpu_base)
		{
		struct gic_chip_data *gic;

		BUG_ON(gic_nr >= MAX_GIC_NR);

		gic = &gic_data[gic_nr];
		gic->dist_base = dist_base;
		gic->cpu_base = cpu_base;
		gic->irq_offset = (irq_start - 1) & ~31;

		if (gic_nr == 0)
		gic_cpu_base_addr = cpu_base;

		gic_dist_init(gic, irq_start);
		gic_cpu_init(gic);
		}

		void __cpuinit gic_secondary_init(unsigned int gic_nr)
		{
		BUG_ON(gic_nr >= MAX_GIC_NR);

		gic_cpu_init(&gic_data[gic_nr]);
		}

		void __cpuinit gic_enable_ppi(unsigned int irq)
		{
		unsigned long flags;

		local_irq_save(flags);
		irq_to_desc(irq)->status \|= IRQ_NOPROBE;
		gic_unmask_irq(irq);
		local_irq_restore(flags);
		}

		#ifdef CONFIG_SMP
		void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
		{